mirror of https://github.com/m-labs/artiq.git
fir: add upsample transfer function test
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4c27029be0
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@ -77,14 +77,31 @@ class ParallelTransfer(Transfer):
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yi[:] = (yield from [(yield o) for o in self.dut.o])
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class UpTransfer(ParallelTransfer):
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def drive(self, x):
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x = x.reshape(-1, len(self.dut.o))
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x[:, 1:] = 0
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for xi in x:
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yield self.dut.i.eq(int(xi[0]))
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yield
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def record(self, y):
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for i in range(self.dut.latency):
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yield
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for yi in y.reshape(-1, len(self.dut.o)):
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yield
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yi[:] = (yield from [(yield o) for o in self.dut.o])
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def _main():
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coeff = fir.halfgen4(.4/2, 8)
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coeff_int = [int(round(c * (1 << 16 - 1))) for c in coeff]
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if False:
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coeff = [[int(round((1 << 26) * ci)) for ci in c]
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coeff = [[int(round((1 << 19) * ci)) for ci in c]
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for c in fir.halfgen4_cascade(8, width=.4, order=8)]
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dut = fir.ParallelHBFUpsampler(coeff, width=16, shift=25)
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print(verilog.convert(dut, ios=set([dut.i] + dut.o)))
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dut = fir.ParallelHBFUpsampler(coeff, width=16, shift=18)
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# print(verilog.convert(dut, ios=set([dut.i] + dut.o)))
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tb = UpTransfer(dut)
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elif True:
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dut = fir.ParallelFIR(coeff_int, parallelism=4, width=16)
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# print(verilog.convert(dut, ios=set(dut.i + dut.o)))
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@ -94,7 +111,7 @@ def _main():
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# print(verilog.convert(dut, ios={dut.i, dut.o}))
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tb = Transfer(dut)
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x, y = tb.run(samples=1 << 10, amplitude=.8)
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x, y = tb.run(samples=1 << 10, amplitude=.5)
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tb.analyze(x, y)
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plt.show()
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