mirror of https://github.com/m-labs/artiq.git
ad9910: add docs for sync tuning, refactor
Signed-off-by: Robert Jördens <rj@quartiq.de>
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7b92282012
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@ -150,7 +150,7 @@ class AD9910:
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raise ValueError("Urukul AD9910 AUX_DAC mismatch")
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delay(50*us) # slack
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# Configure PLL settings and bring up PLL
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self.write32(_AD9910_REG_CFR2, 0x01000020)
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self.write32(_AD9910_REG_CFR2, 0x01010020)
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self.cpld.io_update.pulse(1*us)
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cfr3 = (0x0807c100 | (self.pll_vco << 24) |
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(self.pll_cp << 19) | (self.pll_n << 1))
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@ -256,22 +256,53 @@ class AD9910:
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self.cpld.cfg_sw(self.chip_select - 4, state)
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@kernel
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def set_sync(self, in_delay, window, preset=0):
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def set_sync(self, in_delay, window):
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"""Set the relevant parameters in the multi device synchronization
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register. See the AD9910 datasheet for details. The SYNC clock
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generator preset value is set to zero, and the SYNC_OUT generator is
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disabled.
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:param in_delay: SYNC_IN delay tap (0-31) in steps of ~75ps
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:param window: Symmetric SYNC_IN validation window (0-15) in
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steps of ~75ps for both hold and setup margin.
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"""
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self.write32(_AD9910_REG_MSYNC,
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(window << 28) | # SYNC S/H validation delay
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(1 << 27) | # SYNC receiver enable
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(0 << 26) | # SYNC generator disable
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(0 << 25) | # SYNC generator SYS rising edge
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(preset << 18) | # SYNC preset
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(0 << 18) | # SYNC preset
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(0 << 11) | # SYNC output delay
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(in_delay << 3)) # SYNC receiver delay
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self.write32(_AD9910_REG_CFR2, 0x01000020) # clear SMP_ERR
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@kernel
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def clear_smp_err(self):
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"""Clears the SMP_ERR flag and enables SMP_ERR validity monitoring.
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Violations of the SYNC_IN sample and hold margins will result in
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SMP_ERR being asserted. This then also activates the red LED on
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the respective Urukul channel.
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Also modifies CFR2.
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"""
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self.write32(_AD9910_REG_CFR2, 0x01010020) # clear SMP_ERR
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self.cpld.io_update.pulse(1*us)
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self.write32(_AD9910_REG_CFR2, 0x01000000) # enable SMP_ERR
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self.write32(_AD9910_REG_CFR2, 0x01010000) # enable SMP_ERR
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self.cpld.io_update.pulse(1*us)
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@kernel
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def tune_sync_delay(self):
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"""Find a stable SYNC_IN delay.
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This method first locates the smallest SYNC_IN validity window at
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minimum window size and then increases the window a bit to provide some
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slack and stability.
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It starts scanning delays around :attr:`sync_delay_seed` (see the
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device database arguments and :meth:`__init__`) at maximum validation window
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size and decreases the window size until a valid delay is found.
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:return: Tuple of optimal delay and window size.
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"""
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dt = 14 # 1/(f_SYSCLK*75ps) taps per SYSCLK period
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max_delay = dt # 14*75ps > 1ns
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max_window = dt//4 + 1 # 2*75ps*4 = 600ps high > 1ns/2
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@ -282,8 +313,13 @@ class AD9910:
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# alternate search direction around seed_delay
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if in_delay & 1:
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in_delay = -in_delay
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in_delay = (self.sync_delay_seed + (in_delay >> 1)) & 0x1f
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in_delay = self.sync_delay_seed + (in_delay >> 1)
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if in_delay < 0:
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in_delay = 0
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elif in_delay > 31:
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in_delay = 31
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self.set_sync(in_delay, window)
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self.clear_smp_err()
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# integrate SMP_ERR statistics for a few hundred cycles
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delay(10*us)
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err = urukul_sta_smp_err(self.cpld.sta_read())
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@ -292,5 +328,7 @@ class AD9910:
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if not err:
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window -= min_window # add margin
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self.set_sync(in_delay, window)
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return window, in_delay
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self.clear_smp_err()
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delay(40*us) # slack
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return in_delay, window
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raise ValueError("no valid window/delay")
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