mirror of https://github.com/m-labs/artiq.git
llvm_ir_generator: handle no-op coercions.
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@ -848,6 +848,8 @@ class LLVMIRGenerator:
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def process_Coerce(self, insn):
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def process_Coerce(self, insn):
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typ, value_typ = insn.type, insn.value().type
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typ, value_typ = insn.type, insn.value().type
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if typ == value_typ:
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return self.map(insn.value())
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if builtins.is_int(typ) and builtins.is_float(value_typ):
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if builtins.is_int(typ) and builtins.is_float(value_typ):
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return self.llbuilder.fptosi(self.map(insn.value()), self.llty_of_type(typ),
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return self.llbuilder.fptosi(self.map(insn.value()), self.llty_of_type(typ),
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name=insn.name)
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name=insn.name)
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@ -0,0 +1,4 @@
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# RUN: %python -m artiq.compiler.testbench.llvmgen %s
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def f():
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return float(1.0)
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