From 78e1b9f8e55d5b0d171dfbc983da4f12be83af97 Mon Sep 17 00:00:00 2001 From: Etienne Wodey Date: Fri, 29 Jan 2021 18:47:40 +0100 Subject: [PATCH] sinara_tester/mirny: remove hw_rev checking fixup code Signed-off-by: Etienne Wodey --- artiq/frontend/artiq_sinara_tester.py | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/artiq/frontend/artiq_sinara_tester.py b/artiq/frontend/artiq_sinara_tester.py index 0122df925..c0dca63e9 100755 --- a/artiq/frontend/artiq_sinara_tester.py +++ b/artiq/frontend/artiq_sinara_tester.py @@ -291,18 +291,7 @@ class SinaraTester(EnvExperiment): @kernel def init_mirny(self, cpld): self.core.break_realtime() - # Taken from Mirny.init(), to accomodate Mirny v1.1 without blinding - reg0 = cpld.read_reg(0) - if reg0 & 0b11 != 0b10: # Modified part - raise ValueError("Mirny HW_REV mismatch") - if (reg0 >> 2) & 0b11 != 0b00: - raise ValueError("Mirny PROTO_REV mismatch") - delay(100 * us) # slack - - # select clock source - cpld.write_reg(1, (cpld.clk_sel << 4)) - delay(1000 * us) - # End of modified Mirny.init() + cpld.init() @kernel def setup_mirny(self, channel, frequency):