M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

pdq2: memory write, kernel_invariants

This commit is contained in:
Robert Jördens 2017-04-08 10:38:32 +02:00
parent 16b7f8f50c
commit 78dd4b8614
1 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
artiq/coredevice/pdq2.py
View File

@ -1,5 +1,4 @@
from artiq.language.core import (kernel, portable, delay_mu, delay) from artiq.language.core import kernel, portable, delay_mu
from artiq.language.units import ns, us
from artiq.coredevice import spi from artiq.coredevice import spi
@ -28,6 +27,8 @@ class PDQ2:
during transactions. during transactions.
""" """
kernel_invariants = {"core", "chip_select", "bus"}
def __init__(self, dmgr, spi_device, chip_select=1): def __init__(self, dmgr, spi_device, chip_select=1):
self.core = dmgr.get("core") self.core = dmgr.get("core")
self.bus = dmgr.get(spi_device) self.bus = dmgr.get(spi_device)
@ -66,7 +67,10 @@ class PDQ2:
return self.bus.input_async() & 0xff return self.bus.input_async() & 0xff
@kernel @kernel
def write_config(self, config, board=0xf): def write_config(self, reset=0, clk2x=0, enable=1,
trigger=0, aux_miso=0, aux_dac=0b111, board=0xf):
config = ((reset << 0) | (clk2x << 1) | (enable << 2) |
(trigger << 3) | (aux_miso << 4) | (aux_dac << 5))
self.write_reg(_PDQ2_ADR_CONFIG, config, board) self.write_reg(_PDQ2_ADR_CONFIG, config, board)
@kernel @kernel
@ -97,7 +101,7 @@ class PDQ2:
delay_mu(3*self.bus.ref_period_mu - self.bus.xfer_period_mu - delay_mu(3*self.bus.ref_period_mu - self.bus.xfer_period_mu -
self.bus.write_period_mu) self.bus.write_period_mu)
self.bus.set_xfer(self.chip_select, 16, 0) self.bus.set_xfer(self.chip_select, 16, 0)
for i in len(data)//2: for i in range(len(data)//2):
self.bus.write((data[2*i] << 24) | (data[2*i + 1] << 16)) self.bus.write((data[2*i] << 24) | (data[2*i + 1] << 16))
delay_mu(-self.bus.write_period_mu) delay_mu(-self.bus.write_period_mu)
delay_mu(self.bus.write_period_mu + self.bus.ref_period_mu) delay_mu(self.bus.write_period_mu + self.bus.ref_period_mu)