From 78daace19a42537ce3648a7640f5d913a5c011ea Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Sun, 15 Jan 2023 12:30:08 +0800
Subject: [PATCH] ad9910: fix pll_en doc

---
 artiq/coredevice/ad9910.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py
index 3d6f882c5..e2600d6ac 100644
--- a/artiq/coredevice/ad9910.py
+++ b/artiq/coredevice/ad9910.py
@@ -127,7 +127,7 @@ class AD9910:
         f_ref/clk_div*pll_n where f_ref is the reference frequency and
         clk_div is the reference clock divider (both set in the parent
         Urukul CPLD instance).
-    :param pll_en: PLL enable bit, set to 0 to bypass PLL (default: 1).
+    :param pll_en: PLL enable bit, set to False to bypass PLL (default: True).
         Note that when bypassing the PLL the red front panel LED may remain on.
     :param pll_cp: DDS PLL charge pump setting.
     :param pll_vco: DDS PLL VCO range selection.