mirror of https://github.com/m-labs/artiq.git
gateware/targets: expose variant lists
This allows writing scripts that build all variants.
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parent
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commit
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@ -1123,24 +1123,26 @@ class VLBAISatellite(_SatelliteBase):
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self.add_rtio(self.rtio_channels)
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VARIANTS = {cls.__name__.lower(): cls for cls in [
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Opticlock, SUServo, PTB, PTB2, HUB, LUH,
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SYSU, MITLL, MITLL2, USTC, Tsinghua, Tsinghua2, WIPM, NUDT,
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VLBAIMaster, VLBAISatellite, Tester, Master, Satellite]}
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ device binary builder for Kasli systems")
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builder_args(parser)
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soc_kasli_args(parser)
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parser.set_defaults(output_dir="artiq_kasli")
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variants = {cls.__name__.lower(): cls for cls in [
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Opticlock, SUServo, PTB, PTB2, HUB, LUH,
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SYSU, MITLL, MITLL2, USTC, Tsinghua, Tsinghua2, WIPM, NUDT,
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VLBAIMaster, VLBAISatellite, Tester, Master, Satellite]}
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parser.add_argument("-V", "--variant", default="opticlock",
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help="variant: {} (default: %(default)s)".format(
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"/".join(sorted(variants.keys()))))
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"/".join(sorted(VARIANTS.keys()))))
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args = parser.parse_args()
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variant = args.variant.lower()
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try:
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cls = variants[variant]
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cls = VARIANTS[variant]
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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@ -400,6 +400,9 @@ class SMA_SPI(_StandaloneBase):
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self.csr_devices.append("rtio_analyzer")
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VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_QC2, SMA_SPI]}
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def main():
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parser = argparse.ArgumentParser(
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description="KC705 gateware and firmware builder")
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@ -413,13 +416,9 @@ def main():
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args = parser.parse_args()
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variant = args.variant.lower()
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if variant == "nist_clock":
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cls = NIST_CLOCK
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elif variant == "nist_qc2":
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cls = NIST_QC2
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elif variant == "sma_spi":
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cls = SMA_SPI
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else:
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try:
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cls = VARIANTS[variant]
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls(**soc_kc705_argdict(args))
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