M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

sawg: fix PhasedAccu resets

This commit is contained in:
Robert Jördens 2017-07-04 11:56:01 +02:00
parent 42476c64a7
commit 78d1f0fdf6
2 changed files with 5 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/gateware/dsp/accu.py
View File

@ -74,14 +74,12 @@ class PhasedAccu(Module):
a = MCM(width, range(parallelism + 1)) a = MCM(width, range(parallelism + 1))
self.submodules += a self.submodules += a
z = [Signal(width) for i in range(parallelism)] z = [Signal(width, reset_less=True) for i in range(parallelism)]
o = self.o.payload.flatten() o = self.o.payload.flatten()
for oi in o: load = Signal(reset_less=True)
oi.reset_less = True clr = Signal(reset_less=True)
load = Signal()
clr = Signal()
p = Signal.like(self.i.p) p = Signal.like(self.i.p)
f = Signal.like(self.i.f) f = Signal.like(self.i.f, reset_less=True)
fp = Signal.like(self.i.f) fp = Signal.like(self.i.f)
self.comb += [ self.comb += [
self.i.ack.eq(self.o.ack), self.i.ack.eq(self.o.ack),

1
artiq/gateware/dsp/sawg.py
View File

@ -56,6 +56,7 @@ class SplineParallelDUC(Module):
] ]
assert p.latency == 1 assert p.latency == 1
accu.i.clr.reset_less = True
self.sync += [ self.sync += [
accu.i.clr.eq(0), accu.i.clr.eq(0),
If(p.i.stb, If(p.i.stb,