zotino: style, use attributes to set SPI config

This commit is contained in:
Robert Jördens 2018-03-24 15:37:34 +01:00
parent 22557294ac
commit 77bcc2c78f
2 changed files with 4 additions and 5 deletions

View File

@ -13,7 +13,6 @@ from artiq.language.core import (kernel, portable, delay_mu, delay, now_mu,
from artiq.language.units import ns from artiq.language.units import ns
from artiq.coredevice import spi2 as spi from artiq.coredevice import spi2 as spi
SPI_AD53XX_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END | SPI_AD53XX_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY | 0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE | 0*spi.SPI_CLK_POLARITY | 1*spi.SPI_CLK_PHASE |

View File

@ -8,7 +8,6 @@ from artiq.language.core import kernel
from artiq.coredevice import spi2 as spi from artiq.coredevice import spi2 as spi
from artiq.coredevice.ad53xx import SPI_AD53XX_CONFIG, AD53xx from artiq.coredevice.ad53xx import SPI_AD53XX_CONFIG, AD53xx
_SPI_DAC_CONFIG = SPI_AD53XX_CONFIG
_SPI_SR_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END | _SPI_SR_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY | 0*spi.SPI_INPUT | 0*spi.SPI_CS_POLARITY |
0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE | 0*spi.SPI_CLK_POLARITY | 0*spi.SPI_CLK_PHASE |
@ -17,6 +16,7 @@ _SPI_SR_CONFIG = (0*spi.SPI_OFFLINE | 1*spi.SPI_END |
_SPI_CS_DAC = 1 _SPI_CS_DAC = 1
_SPI_CS_SR = 2 _SPI_CS_SR = 2
class Zotino(AD53xx): class Zotino(AD53xx):
""" Zotino 32-channel, 16-bit 1MSPS DAC. """ Zotino 32-channel, 16-bit 1MSPS DAC.
@ -49,5 +49,5 @@ class Zotino(AD53xx):
""" """
self.bus.set_config_mu(_SPI_SR_CONFIG, 8, self.div_write, _SPI_CS_SR) self.bus.set_config_mu(_SPI_SR_CONFIG, 8, self.div_write, _SPI_CS_SR)
self.bus.write(leds << 24) self.bus.write(leds << 24)
self.bus.set_config_mu(_SPI_DAC_CONFIG, 24, self.div_write, self.bus.set_config_mu(SPI_AD53XX_CONFIG, 24, self.div_write,
_SPI_CS_DAC) self.chip_select)