From 771bf87b562823ed06362137ba23f654cfa2f927 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Thu, 22 Feb 2018 10:55:50 +0000 Subject: [PATCH] kc705: port amc101_dac/spi0 and sma_spi to spi2 --- artiq/examples/kc705_nist_clock/device_db.py | 4 ++-- artiq/gateware/targets/kc705.py | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/artiq/examples/kc705_nist_clock/device_db.py b/artiq/examples/kc705_nist_clock/device_db.py index e8e0901f1..24958a56d 100644 --- a/artiq/examples/kc705_nist_clock/device_db.py +++ b/artiq/examples/kc705_nist_clock/device_db.py @@ -119,7 +119,7 @@ device_db = { # Generic SPI "spi0": { "type": "local", - "module": "artiq.coredevice.spi", + "module": "artiq.coredevice.spi2", "class": "SPIMaster", "arguments": {"channel": 23} }, @@ -161,7 +161,7 @@ device_db = { # DAC "spi_ams101": { "type": "local", - "module": "artiq.coredevice.spi", + "module": "artiq.coredevice.spi2", "class": "SPIMaster", "arguments": {"channel": 22} }, diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index e19ce222b..5d171f053 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -319,7 +319,7 @@ class NIST_CLOCK(_StandaloneBase): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - phy = spi.SPIMaster(ams101_dac) + phy = spi2.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=4)) @@ -423,7 +423,7 @@ class NIST_QC2(_StandaloneBase): # add clock generators after TTLs rtio_channels += clock_generators - phy = spi.SPIMaster(ams101_dac) + phy = spi2.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=4)) @@ -478,12 +478,12 @@ class SMA_SPI(_StandaloneBase): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy)) - phy = spi.SPIMaster(ams101_dac) + phy = spi2.SPIMaster(ams101_dac) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=4)) - phy = spi.SPIMaster(self.platform.request("sma_spi")) + phy = spi2.SPIMaster(self.platform.request("sma_spi")) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ififo_depth=128))