From 76d704ac332ff665ddce7a8d56d4dc88d467fef9 Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 16 Apr 2024 10:22:18 +0800 Subject: [PATCH] drtio: revert async flag message --- artiq/gateware/drtio/core.py | 6 +----- artiq/gateware/drtio/rt_controller_master.py | 6 ------ artiq/gateware/drtio/rt_controller_repeater.py | 7 ------- artiq/gateware/drtio/rt_packet_master.py | 7 ------- artiq/gateware/drtio/rt_packet_repeater.py | 4 +--- artiq/gateware/drtio/rt_packet_satellite.py | 12 ------------ artiq/gateware/drtio/rt_serializer.py | 1 - 7 files changed, 2 insertions(+), 41 deletions(-) diff --git a/artiq/gateware/drtio/core.py b/artiq/gateware/drtio/core.py index b344b9c95..c6db5d9af 100644 --- a/artiq/gateware/drtio/core.py +++ b/artiq/gateware/drtio/core.py @@ -78,7 +78,6 @@ class DRTIOSatellite(Module): self.reset = CSRStorage(reset=1) self.reset_phy = CSRStorage(reset=1) self.tsc_loaded = CSR() - self.async_messages_ready = CSR() # master interface in the sys domain self.cri = cri.Interface() self.async_errors = Record(async_errors_layout) @@ -130,9 +129,6 @@ class DRTIOSatellite(Module): link_layer_sync, interface=self.cri) self.comb += self.rt_packet.reset.eq(self.cd_rio.rst) - self.sync += If(self.async_messages_ready.re, self.rt_packet.async_msg_stb.eq(1)) - self.comb += self.async_messages_ready.w.eq(self.rt_packet.async_msg_ack) - self.comb += [ tsc.load.eq(self.rt_packet.tsc_load), tsc.load_value.eq(self.rt_packet.tsc_load_value) @@ -147,7 +143,7 @@ class DRTIOSatellite(Module): self.rt_packet, tsc, self.async_errors) def get_csrs(self): - return ([self.reset, self.reset_phy, self.tsc_loaded, self.async_messages_ready] + + return ([self.reset, self.reset_phy, self.tsc_loaded] + self.link_layer.get_csrs() + self.link_stats.get_csrs() + self.rt_errors.get_csrs()) diff --git a/artiq/gateware/drtio/rt_controller_master.py b/artiq/gateware/drtio/rt_controller_master.py index aa630254f..3ed22dbe7 100644 --- a/artiq/gateware/drtio/rt_controller_master.py +++ b/artiq/gateware/drtio/rt_controller_master.py @@ -17,7 +17,6 @@ class _CSRs(AutoCSR): self.set_time = CSR() self.underflow_margin = CSRStorage(16, reset=300) - self.async_messages_ready = CSR() self.force_destination = CSRStorage() self.destination = CSRStorage(8) @@ -61,11 +60,6 @@ class RTController(Module): If(self.csrs.set_time.re, rt_packet.set_time_stb.eq(1)) ] - self.sync += [ - If(rt_packet.async_messages_ready, self.csrs.async_messages_ready.w.eq(1)), - If(self.csrs.async_messages_ready.re, self.csrs.async_messages_ready.w.eq(0)) - ] - # chan_sel forcing chan_sel = Signal(24) self.comb += chan_sel.eq(Mux(self.csrs.force_destination.storage, diff --git a/artiq/gateware/drtio/rt_controller_repeater.py b/artiq/gateware/drtio/rt_controller_repeater.py index bdc96fe38..79b9559eb 100644 --- a/artiq/gateware/drtio/rt_controller_repeater.py +++ b/artiq/gateware/drtio/rt_controller_repeater.py @@ -14,7 +14,6 @@ class RTController(Module, AutoCSR): self.command_missed_cmd = CSRStatus(2) self.command_missed_chan_sel = CSRStatus(24) self.buffer_space_timeout_dest = CSRStatus(8) - self.async_messages_ready = CSR() self.sync += rt_packet.reset.eq(self.reset.storage) @@ -24,12 +23,6 @@ class RTController(Module, AutoCSR): ] self.comb += self.set_time.w.eq(rt_packet.set_time_stb) - self.sync += [ - If(rt_packet.async_messages_ready, self.async_messages_ready.w.eq(1)), - If(self.async_messages_ready.re, self.async_messages_ready.w.eq(0)) - ] - - errors = [ (rt_packet.err_unknown_packet_type, "rtio_rx", None, None), (rt_packet.err_packet_truncated, "rtio_rx", None, None), diff --git a/artiq/gateware/drtio/rt_packet_master.py b/artiq/gateware/drtio/rt_packet_master.py index 32d3a39a7..70d44ecaf 100644 --- a/artiq/gateware/drtio/rt_packet_master.py +++ b/artiq/gateware/drtio/rt_packet_master.py @@ -61,9 +61,6 @@ class RTPacketMaster(Module): # a set_time request pending self.tsc_value = Signal(64) - # async aux messages interface, only received - self.async_messages_ready = Signal() - # rx errors self.err_unknown_packet_type = Signal() self.err_packet_truncated = Signal() @@ -286,16 +283,12 @@ class RTPacketMaster(Module): echo_received_now = Signal() self.sync.rtio_rx += self.echo_received_now.eq(echo_received_now) - async_messages_ready = Signal() - self.sync.rtio_rx += self.async_messages_ready.eq(async_messages_ready) - rx_fsm.act("INPUT", If(rx_dp.frame_r, rx_dp.packet_buffer_load.eq(1), If(rx_dp.packet_last, Case(rx_dp.packet_type, { rx_plm.types["echo_reply"]: echo_received_now.eq(1), - rx_plm.types["async_messages_ready"]: async_messages_ready.eq(1), rx_plm.types["buffer_space_reply"]: NextState("BUFFER_SPACE"), rx_plm.types["read_reply"]: NextState("READ_REPLY"), rx_plm.types["read_reply_noevent"]: NextState("READ_REPLY_NOEVENT"), diff --git a/artiq/gateware/drtio/rt_packet_repeater.py b/artiq/gateware/drtio/rt_packet_repeater.py index 62abeeee1..728c24ae8 100644 --- a/artiq/gateware/drtio/rt_packet_repeater.py +++ b/artiq/gateware/drtio/rt_packet_repeater.py @@ -19,7 +19,6 @@ class RTPacketRepeater(Module): # in rtio_rx domain self.err_unknown_packet_type = Signal() self.err_packet_truncated = Signal() - self.async_messages_ready = Signal() # in rtio domain self.err_command_missed = Signal() @@ -305,7 +304,6 @@ class RTPacketRepeater(Module): rx_dp.packet_buffer_load.eq(1), If(rx_dp.packet_last, Case(rx_dp.packet_type, { - rx_plm.types["async_messages_ready"]: self.async_messages_ready.eq(1), rx_plm.types["buffer_space_reply"]: NextState("BUFFER_SPACE"), rx_plm.types["read_reply"]: NextState("READ_REPLY"), rx_plm.types["read_reply_noevent"]: NextState("READ_REPLY_NOEVENT"), @@ -333,4 +331,4 @@ class RTPacketRepeater(Module): read_not.eq(1), read_no_event.eq(1), NextState("INPUT") - ) \ No newline at end of file + ) diff --git a/artiq/gateware/drtio/rt_packet_satellite.py b/artiq/gateware/drtio/rt_packet_satellite.py index a4094d9db..79a48f493 100644 --- a/artiq/gateware/drtio/rt_packet_satellite.py +++ b/artiq/gateware/drtio/rt_packet_satellite.py @@ -19,9 +19,6 @@ class RTPacketSatellite(Module): self.tsc_load = Signal() self.tsc_load_value = Signal(64) - self.async_msg_stb = Signal() - self.async_msg_ack = Signal() - if interface is None: interface = cri.Interface() self.cri = interface @@ -81,8 +78,6 @@ class RTPacketSatellite(Module): ) ] - self.sync += If(self.async_msg_ack, self.async_msg_stb.eq(0)) - # RX FSM cri_read = Signal() cri_buffer_space = Signal() @@ -202,7 +197,6 @@ class RTPacketSatellite(Module): tx_fsm.act("IDLE", If(echo_req, NextState("ECHO")), - If(self.async_msg_stb, NextState("ASYNC_MESSAGES_READY")), If(buffer_space_req, NextState("BUFFER_SPACE")), If(read_request_pending & ~self.cri.i_status[2], NextState("READ"), @@ -216,12 +210,6 @@ class RTPacketSatellite(Module): If(tx_dp.packet_last, NextState("IDLE")) ) - tx_fsm.act("ASYNC_MESSAGES_READY", - self.async_msg_ack.eq(1), - tx_dp.send("async_messages_ready"), - If(tx_dp.packet_last, NextState("IDLE")) - ) - tx_fsm.act("BUFFER_SPACE", buffer_space_ack.eq(1), tx_dp.send("buffer_space_reply", space=buffer_space), diff --git a/artiq/gateware/drtio/rt_serializer.py b/artiq/gateware/drtio/rt_serializer.py index 9a77263a4..01e5cf19e 100644 --- a/artiq/gateware/drtio/rt_serializer.py +++ b/artiq/gateware/drtio/rt_serializer.py @@ -69,7 +69,6 @@ def get_s2m_layouts(alignment): plm.add_type("read_reply", ("timestamp", 64), ("data", 32)) plm.add_type("read_reply_noevent", ("overflow", 1)) # overflow=0→timeout - plm.add_type("async_messages_ready") return plm