mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 03:08:27 +08:00
firmware: split libdrtioaux into libproto and libboard_artiq modules.
All other protocol code lives in libproto, and all other gateware interfaces live in libboard_artiq.
This commit is contained in:
parent
6a10d54432
commit
764386c9e3
16
artiq/firmware/Cargo.lock
generated
16
artiq/firmware/Cargo.lock
generated
@ -35,7 +35,10 @@ dependencies = [
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"build_artiq 0.0.0",
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"build_misoc 0.0.0",
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"byteorder 1.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"crc 1.7.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"io 0.0.0",
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"log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
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"proto 0.0.0",
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]
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[[package]]
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@ -98,17 +101,6 @@ name = "cslice"
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version = "0.3.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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name = "drtioaux"
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version = "0.0.0"
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dependencies = [
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"board 0.0.0",
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"build_misoc 0.0.0",
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"crc 1.7.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"io 0.0.0",
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"log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "dyld"
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version = "0.0.0"
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@ -219,7 +211,6 @@ dependencies = [
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"build_misoc 0.0.0",
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"byteorder 1.2.2 (registry+https://github.com/rust-lang/crates.io-index)",
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"cslice 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"drtioaux 0.0.0",
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"fringe 1.1.0 (git+https://github.com/m-labs/libfringe?rev=bd23494)",
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"io 0.0.0",
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"log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
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@ -248,7 +239,6 @@ dependencies = [
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"board_artiq 0.0.0",
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"build_artiq 0.0.0",
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"build_misoc 0.0.0",
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"drtioaux 0.0.0",
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"log 0.4.1 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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@ -15,7 +15,10 @@ build_artiq = { path = "../libbuild_artiq" }
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[dependencies]
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bitflags = "1.0"
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byteorder = { version = "1.0", default-features = false }
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crc = { version = "1.7", default-features = false }
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log = { version = "0.4", default-features = false }
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io = { path = "../libio", features = ["byteorder"] }
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proto = { path = "../libproto" }
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board = { path = "../libboard" }
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[features]
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@ -1,8 +1,11 @@
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use core::fmt;
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use io::{Cursor, Error as IoError};
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use io::proto::ProtoRead;
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use core::{slice, fmt, result};
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use crc;
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use super::*;
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use io::{Cursor, Error as IoError};
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use io::proto::{ProtoRead, ProtoWrite};
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use board;
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pub use proto::drtioaux_proto::Packet;
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pub type Result<T> = result::Result<T, Error>;
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@ -1,12 +1,15 @@
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#![feature(asm, lang_items)]
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#![feature(asm, lang_items, never_type)]
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#![no_std]
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#[macro_use]
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extern crate bitflags;
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extern crate byteorder;
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extern crate crc;
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#[macro_use]
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extern crate log;
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extern crate board;
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extern crate io;
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extern crate proto;
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pub mod pcr;
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@ -28,3 +31,6 @@ mod ad9154_reg;
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pub mod ad9154;
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#[cfg(has_allaki_atts)]
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pub mod hmc542;
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#[cfg(has_drtio)]
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pub mod drtioaux;
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@ -1,18 +0,0 @@
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[package]
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authors = ["M-Labs"]
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name = "drtioaux"
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version = "0.0.0"
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build = "build.rs"
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[lib]
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name = "drtioaux"
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path = "lib.rs"
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[build-dependencies]
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build_misoc = { path = "../libbuild_misoc" }
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[dependencies]
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log = { version = "0.4", default-features = false }
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crc = { version = "1.7", default-features = false }
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io = { path = "../libio", features = ["byteorder"] }
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board = { path = "../libboard" }
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@ -1,5 +0,0 @@
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extern crate build_misoc;
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fn main() {
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build_misoc::cfg();
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}
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@ -1,11 +1,3 @@
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#![no_std]
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#![feature(never_type)]
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extern crate crc;
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extern crate io;
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extern crate board;
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use io::{Read, Write, Error, Result};
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use io::proto::{ProtoRead, ProtoWrite};
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@ -264,6 +256,3 @@ impl Packet {
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Ok(())
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}
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}
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#[cfg(has_drtio)]
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pub mod hw;
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@ -13,6 +13,7 @@ extern crate dyld;
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// Internal protocols.
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pub mod kernel_proto;
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pub mod drtioaux_proto;
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// External protocols.
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#[cfg(feature = "alloc")]
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@ -27,7 +27,6 @@ logger_artiq = { path = "../liblogger_artiq" }
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board_artiq = { path = "../libboard_artiq" }
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proto = { path = "../libproto", features = ["log", "alloc"] }
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amp = { path = "../libamp" }
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drtioaux = { path = "../libdrtioaux" }
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[dependencies.fringe]
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git = "https://github.com/m-labs/libfringe"
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@ -10,7 +10,7 @@ mod drtio_i2c {
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use drtioaux;
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fn basic_reply(nodeno: u8) -> Result<(), ()> {
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match drtioaux::hw::recv_timeout(nodeno, None) {
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match drtioaux::recv_timeout(nodeno, None) {
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Ok(drtioaux::Packet::I2cBasicReply { succeeded }) => {
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if succeeded { Ok(()) } else { Err(()) }
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}
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@ -27,7 +27,7 @@ mod drtio_i2c {
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pub fn start(nodeno: u8, busno: u8) -> Result<(), ()> {
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let request = drtioaux::Packet::I2cStartRequest { busno: busno };
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if drtioaux::hw::send(nodeno, &request).is_err() {
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if drtioaux::send(nodeno, &request).is_err() {
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return Err(())
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}
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basic_reply(nodeno)
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@ -35,7 +35,7 @@ mod drtio_i2c {
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pub fn restart(nodeno: u8, busno: u8) -> Result<(), ()> {
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let request = drtioaux::Packet::I2cRestartRequest { busno: busno };
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if drtioaux::hw::send(nodeno, &request).is_err() {
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if drtioaux::send(nodeno, &request).is_err() {
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return Err(())
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}
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basic_reply(nodeno)
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@ -43,7 +43,7 @@ mod drtio_i2c {
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pub fn stop(nodeno: u8, busno: u8) -> Result<(), ()> {
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let request = drtioaux::Packet::I2cStopRequest { busno: busno };
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if drtioaux::hw::send(nodeno, &request).is_err() {
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if drtioaux::send(nodeno, &request).is_err() {
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return Err(())
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}
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basic_reply(nodeno)
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@ -54,10 +54,10 @@ mod drtio_i2c {
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busno: busno,
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data: data
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};
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if drtioaux::hw::send(nodeno, &request).is_err() {
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if drtioaux::send(nodeno, &request).is_err() {
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return Err(())
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}
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match drtioaux::hw::recv_timeout(nodeno, None) {
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match drtioaux::recv_timeout(nodeno, None) {
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Ok(drtioaux::Packet::I2cWriteReply { succeeded, ack }) => {
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if succeeded { Ok(ack) } else { Err(()) }
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}
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@ -77,10 +77,10 @@ mod drtio_i2c {
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busno: busno,
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ack: ack
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};
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if drtioaux::hw::send(nodeno, &request).is_err() {
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if drtioaux::send(nodeno, &request).is_err() {
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return Err(())
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}
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match drtioaux::hw::recv_timeout(nodeno, None) {
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match drtioaux::recv_timeout(nodeno, None) {
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Ok(drtioaux::Packet::I2cReadReply { succeeded, data }) => {
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if succeeded { Ok(data) } else { Err(()) }
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}
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@ -179,7 +179,7 @@ mod drtio_spi {
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use drtioaux;
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fn basic_reply(nodeno: u8) -> Result<(), ()> {
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match drtioaux::hw::recv_timeout(nodeno, None) {
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match drtioaux::recv_timeout(nodeno, None) {
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Ok(drtioaux::Packet::SpiBasicReply { succeeded }) => {
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if succeeded { Ok(()) } else { Err(()) }
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}
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@ -202,7 +202,7 @@ mod drtio_spi {
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div: div,
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cs: cs
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};
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if drtioaux::hw::send(nodeno, &request).is_err() {
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if drtioaux::send(nodeno, &request).is_err() {
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return Err(())
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}
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basic_reply(nodeno)
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@ -213,7 +213,7 @@ mod drtio_spi {
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busno: busno,
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data: data
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};
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if drtioaux::hw::send(nodeno, &request).is_err() {
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if drtioaux::send(nodeno, &request).is_err() {
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return Err(())
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}
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basic_reply(nodeno)
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@ -221,10 +221,10 @@ mod drtio_spi {
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pub fn read(nodeno: u8, busno: u8) -> Result<u32, ()> {
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let request = drtioaux::Packet::SpiReadRequest { busno: busno };
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if drtioaux::hw::send(nodeno, &request).is_err() {
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if drtioaux::send(nodeno, &request).is_err() {
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return Err(())
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}
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match drtioaux::hw::recv_timeout(nodeno, None) {
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match drtioaux::recv_timeout(nodeno, None) {
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Ok(drtioaux::Packet::SpiReadReply { succeeded, data }) => {
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if succeeded { Ok(data) } else { Err(()) }
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}
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@ -21,8 +21,6 @@ extern crate board;
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extern crate board_artiq;
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extern crate proto;
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extern crate amp;
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#[cfg(has_drtio)]
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extern crate drtioaux;
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use core::convert::TryFrom;
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use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
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@ -31,7 +29,11 @@ use board::irq;
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use board::config;
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#[cfg(has_ethmac)]
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use board::ethmac;
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use proto::{mgmt_proto, analyzer_proto, moninj_proto, rpc_proto, session_proto, kernel_proto};
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#[cfg(has_drtio)]
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use board_artiq::drtioaux;
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use proto::{mgmt_proto, moninj_proto, rpc_proto, session_proto,kernel_proto};
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#[cfg(has_rtio_analyzer)]
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use proto::analyzer_proto;
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use amp::{mailbox, rpc_queue};
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#[cfg(has_rtio_core)]
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@ -35,14 +35,14 @@ fn read_probe_local(channel: u16, probe: u8) -> u32 {
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#[cfg(has_drtio)]
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fn read_probe_drtio(nodeno: u8, channel: u16, probe: u8) -> u32 {
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let request = drtioaux::Packet::MonitorRequest { channel: channel, probe: probe };
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match drtioaux::hw::send(nodeno, &request) {
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match drtioaux::send(nodeno, &request) {
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Ok(_) => (),
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Err(e) => {
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error!("aux packet error ({})", e);
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return 0;
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}
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}
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match drtioaux::hw::recv_timeout(nodeno, None) {
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match drtioaux::recv_timeout(nodeno, None) {
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Ok(drtioaux::Packet::MonitorReply { value }) => return value,
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Ok(_) => error!("received unexpected aux packet"),
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Err(e) => error!("aux packet error ({})", e)
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@ -85,7 +85,7 @@ fn inject_drtio(nodeno: u8, channel: u16, overrd: u8, value: u8) {
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overrd: overrd,
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value: value
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};
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match drtioaux::hw::send(nodeno, &request) {
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match drtioaux::send(nodeno, &request) {
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Ok(_) => (),
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Err(e) => error!("aux packet error ({})", e)
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}
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@ -126,14 +126,14 @@ fn read_injection_status_drtio(nodeno: u8, channel: u16, overrd: u8) -> u8 {
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channel: channel,
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overrd: overrd
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};
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match drtioaux::hw::send(nodeno, &request) {
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match drtioaux::send(nodeno, &request) {
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Ok(_) => (),
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Err(e) => {
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error!("aux packet error ({})", e);
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return 0;
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}
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}
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match drtioaux::hw::recv_timeout(nodeno, None) {
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match drtioaux::recv_timeout(nodeno, None) {
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Ok(drtioaux::Packet::InjectionStatusReply { value }) => return value,
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Ok(_) => error!("received unexpected aux packet"),
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Err(e) => error!("aux packet error ({})", e)
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@ -99,9 +99,9 @@ pub mod drtio {
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return 0
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}
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count += 1;
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drtioaux::hw::send_link(linkno, &drtioaux::Packet::EchoRequest).unwrap();
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drtioaux::send_link(linkno, &drtioaux::Packet::EchoRequest).unwrap();
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io.sleep(100).unwrap();
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let pr = drtioaux::hw::recv_link(linkno);
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let pr = drtioaux::recv_link(linkno);
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match pr {
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Ok(Some(drtioaux::Packet::EchoReply)) => return count,
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_ => {}
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@ -131,8 +131,8 @@ pub mod drtio {
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}
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fn process_aux_errors(linkno: u8) {
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drtioaux::hw::send_link(linkno, &drtioaux::Packet::RtioErrorRequest).unwrap();
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match drtioaux::hw::recv_timeout_link(linkno, None) {
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drtioaux::send_link(linkno, &drtioaux::Packet::RtioErrorRequest).unwrap();
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match drtioaux::recv_timeout_link(linkno, None) {
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Ok(drtioaux::Packet::RtioNoErrorReply) => (),
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Ok(drtioaux::Packet::RtioErrorSequenceErrorReply { channel }) =>
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error!("[LINK#{}] RTIO sequence error involving channel {}", linkno, channel),
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@ -144,7 +144,7 @@ pub mod drtio {
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Err(e) => error!("[LINK#{}] aux packet error ({})", linkno, e)
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}
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}
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pub fn link_thread(io: Io) {
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loop {
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for linkno in 0..csr::DRTIO.len() {
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@ -183,9 +183,9 @@ pub mod drtio {
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for linkno in 0..csr::DRTIO.len() {
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let linkno = linkno as u8;
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if link_up(linkno) {
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drtioaux::hw::send_link(linkno,
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drtioaux::send_link(linkno,
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&drtioaux::Packet::ResetRequest { phy: false }).unwrap();
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match drtioaux::hw::recv_timeout_link(linkno, None) {
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match drtioaux::recv_timeout_link(linkno, None) {
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Ok(drtioaux::Packet::ResetAck) => (),
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Ok(_) => error!("[LINK#{}] reset failed, received unexpected aux packet", linkno),
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Err(e) => error!("[LINK#{}] reset failed, aux packet error ({})", linkno, e)
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@ -17,4 +17,3 @@ build_artiq = { path = "../libbuild_artiq" }
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log = { version = "0.4", default-features = false }
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board = { path = "../libboard", features = ["uart_console", "log"] }
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board_artiq = { path = "../libboard_artiq" }
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drtioaux = { path = "../libdrtioaux" }
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@ -6,10 +6,9 @@ extern crate log;
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#[macro_use]
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extern crate board;
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extern crate board_artiq;
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extern crate drtioaux;
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use board::csr;
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use board_artiq::{i2c, spi, si5324};
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use board_artiq::{i2c, spi, si5324, drtioaux};
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#[cfg(has_serwb_phy_amc)]
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use board_artiq::serwb;
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#[cfg(has_hmc830_7043)]
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@ -27,12 +26,12 @@ fn drtio_reset_phy(reset: bool) {
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}
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}
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fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
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fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::Result<()> {
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// In the code below, *_chan_sel_write takes an u8 if there are fewer than 256 channels,
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// and u16 otherwise; hence the `as _` conversion.
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match packet {
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drtioaux::Packet::EchoRequest =>
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drtioaux::hw::send_link(0, &drtioaux::Packet::EchoReply),
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drtioaux::send_link(0, &drtioaux::Packet::EchoReply),
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drtioaux::Packet::ResetRequest { phy } => {
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if phy {
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drtio_reset_phy(true);
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@ -41,7 +40,7 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
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drtio_reset(true);
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drtio_reset(false);
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}
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drtioaux::hw::send_link(0, &drtioaux::Packet::ResetAck)
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drtioaux::send_link(0, &drtioaux::Packet::ResetAck)
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},
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||||
|
||||
drtioaux::Packet::RtioErrorRequest => {
|
||||
@ -55,7 +54,7 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
|
||||
channel = (csr::DRTIO[0].sequence_error_channel_read)();
|
||||
(csr::DRTIO[0].rtio_error_write)(1);
|
||||
}
|
||||
drtioaux::hw::send_link(0,
|
||||
drtioaux::send_link(0,
|
||||
&drtioaux::Packet::RtioErrorSequenceErrorReply { channel })
|
||||
} else if errors & 2 != 0 {
|
||||
let channel;
|
||||
@ -63,7 +62,7 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
|
||||
channel = (csr::DRTIO[0].collision_channel_read)();
|
||||
(csr::DRTIO[0].rtio_error_write)(2);
|
||||
}
|
||||
drtioaux::hw::send_link(0,
|
||||
drtioaux::send_link(0,
|
||||
&drtioaux::Packet::RtioErrorCollisionReply { channel })
|
||||
} else if errors & 4 != 0 {
|
||||
let channel;
|
||||
@ -71,11 +70,11 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
|
||||
channel = (board::csr::DRTIO[0].busy_channel_read)();
|
||||
(board::csr::DRTIO[0].rtio_error_write)(4);
|
||||
}
|
||||
drtioaux::hw::send_link(0,
|
||||
drtioaux::send_link(0,
|
||||
&drtioaux::Packet::RtioErrorBusyReply { channel })
|
||||
}
|
||||
else {
|
||||
drtioaux::hw::send_link(0, &drtioaux::Packet::RtioNoErrorReply)
|
||||
drtioaux::send_link(0, &drtioaux::Packet::RtioNoErrorReply)
|
||||
}
|
||||
}
|
||||
|
||||
@ -93,7 +92,7 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
|
||||
value = 0;
|
||||
}
|
||||
let reply = drtioaux::Packet::MonitorReply { value: value as u32 };
|
||||
drtioaux::hw::send_link(0, &reply)
|
||||
drtioaux::send_link(0, &reply)
|
||||
},
|
||||
drtioaux::Packet::InjectionRequest { channel, overrd, value } => {
|
||||
#[cfg(has_rtio_moninj)]
|
||||
@ -116,53 +115,53 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
|
||||
{
|
||||
value = 0;
|
||||
}
|
||||
drtioaux::hw::send_link(0, &drtioaux::Packet::InjectionStatusReply { value: value })
|
||||
drtioaux::send_link(0, &drtioaux::Packet::InjectionStatusReply { value: value })
|
||||
},
|
||||
|
||||
drtioaux::Packet::I2cStartRequest { busno } => {
|
||||
let succeeded = i2c::start(busno).is_ok();
|
||||
drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
|
||||
drtioaux::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
|
||||
}
|
||||
drtioaux::Packet::I2cRestartRequest { busno } => {
|
||||
let succeeded = i2c::restart(busno).is_ok();
|
||||
drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
|
||||
drtioaux::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
|
||||
}
|
||||
drtioaux::Packet::I2cStopRequest { busno } => {
|
||||
let succeeded = i2c::stop(busno).is_ok();
|
||||
drtioaux::hw::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
|
||||
drtioaux::send_link(0, &drtioaux::Packet::I2cBasicReply { succeeded: succeeded })
|
||||
}
|
||||
drtioaux::Packet::I2cWriteRequest { busno, data } => {
|
||||
match i2c::write(busno, data) {
|
||||
Ok(ack) => drtioaux::hw::send_link(0,
|
||||
Ok(ack) => drtioaux::send_link(0,
|
||||
&drtioaux::Packet::I2cWriteReply { succeeded: true, ack: ack }),
|
||||
Err(_) => drtioaux::hw::send_link(0,
|
||||
Err(_) => drtioaux::send_link(0,
|
||||
&drtioaux::Packet::I2cWriteReply { succeeded: false, ack: false })
|
||||
}
|
||||
}
|
||||
drtioaux::Packet::I2cReadRequest { busno, ack } => {
|
||||
match i2c::read(busno, ack) {
|
||||
Ok(data) => drtioaux::hw::send_link(0,
|
||||
Ok(data) => drtioaux::send_link(0,
|
||||
&drtioaux::Packet::I2cReadReply { succeeded: true, data: data }),
|
||||
Err(_) => drtioaux::hw::send_link(0,
|
||||
Err(_) => drtioaux::send_link(0,
|
||||
&drtioaux::Packet::I2cReadReply { succeeded: false, data: 0xff })
|
||||
}
|
||||
}
|
||||
|
||||
drtioaux::Packet::SpiSetConfigRequest { busno, flags, length, div, cs } => {
|
||||
let succeeded = spi::set_config(busno, flags, length, div, cs).is_ok();
|
||||
drtioaux::hw::send_link(0,
|
||||
drtioaux::send_link(0,
|
||||
&drtioaux::Packet::SpiBasicReply { succeeded: succeeded })
|
||||
},
|
||||
drtioaux::Packet::SpiWriteRequest { busno, data } => {
|
||||
let succeeded = spi::write(busno, data).is_ok();
|
||||
drtioaux::hw::send_link(0,
|
||||
drtioaux::send_link(0,
|
||||
&drtioaux::Packet::SpiBasicReply { succeeded: succeeded })
|
||||
}
|
||||
drtioaux::Packet::SpiReadRequest { busno } => {
|
||||
match spi::read(busno) {
|
||||
Ok(data) => drtioaux::hw::send_link(0,
|
||||
Ok(data) => drtioaux::send_link(0,
|
||||
&drtioaux::Packet::SpiReadReply { succeeded: true, data: data }),
|
||||
Err(_) => drtioaux::hw::send_link(0,
|
||||
Err(_) => drtioaux::send_link(0,
|
||||
&drtioaux::Packet::SpiReadReply { succeeded: false, data: 0 })
|
||||
}
|
||||
}
|
||||
@ -176,7 +175,7 @@ fn process_aux_packet(packet: drtioaux::Packet) -> drtioaux::hw::Result<()> {
|
||||
|
||||
fn process_aux_packets() {
|
||||
let result =
|
||||
drtioaux::hw::recv_link(0).and_then(|packet| {
|
||||
drtioaux::recv_link(0).and_then(|packet| {
|
||||
if let Some(packet) = packet {
|
||||
process_aux_packet(packet)
|
||||
} else {
|
||||
@ -267,7 +266,7 @@ pub extern fn main() -> i32 {
|
||||
info!("link is up, switching to recovered clock");
|
||||
si5324::siphaser::select_recovered_clock(true).expect("failed to switch clocks");
|
||||
si5324::siphaser::calibrate_skew(32).expect("failed to calibrate skew");
|
||||
drtioaux::hw::reset(0);
|
||||
drtioaux::reset(0);
|
||||
drtio_reset(false);
|
||||
drtio_reset_phy(false);
|
||||
while drtio_link_rx_up() {
|
||||
|
Loading…
Reference in New Issue
Block a user