From 8da924ec0fb5a1358831510b967753adc344936a Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:28:26 +0800 Subject: [PATCH 01/22] dma: set conversion granularity using bus width --- artiq/gateware/rtio/analyzer.py | 23 +++++------------------ artiq/gateware/rtio/dma.py | 32 ++++++++++++-------------------- 2 files changed, 17 insertions(+), 38 deletions(-) diff --git a/artiq/gateware/rtio/analyzer.py b/artiq/gateware/rtio/analyzer.py index 1818d3c43..ef154affa 100644 --- a/artiq/gateware/rtio/analyzer.py +++ b/artiq/gateware/rtio/analyzer.py @@ -3,6 +3,7 @@ from migen.genlib.record import Record, layout_len from misoc.interconnect.csr import * from misoc.interconnect import stream +from artiq.gateware.rtio import dma from artiq.gateware.rtio.cri import commands as cri_commands from artiq.coredevice.comm_analyzer import MessageType, ExceptionType @@ -42,20 +43,6 @@ assert layout_len(exception_layout) == message_len assert layout_len(stopped_layout) == message_len -def convert_signal(signal): - assert len(signal) % 8 == 0 - nbytes = len(signal)//8 - assert nbytes % 4 == 0 - nwords = nbytes//4 - signal_words = [] - for i in range(nwords): - signal_bytes = [] - for j in range(4): - signal_bytes.append(signal[8*(j+i*4):8*((j+i*4)+1)]) - signal_words.extend(reversed(signal_bytes)) - return Cat(*signal_words) - - class MessageEncoder(Module, AutoCSR): def __init__(self, tsc, cri, enable): self.source = stream.Endpoint([("data", message_len)]) @@ -150,7 +137,7 @@ class MessageEncoder(Module, AutoCSR): class DMAWriter(Module, AutoCSR): - def __init__(self, membus): + def __init__(self, membus, cpu_dw): aw = len(membus.adr) dw = len(membus.dat_w) messages_per_dw = dw//message_len @@ -175,7 +162,7 @@ class DMAWriter(Module, AutoCSR): membus.stb.eq(self.sink.stb), self.sink.ack.eq(membus.ack), membus.we.eq(1), - membus.dat_w.eq(convert_signal(self.sink.data)) + membus.dat_w.eq(dma.convert_signal(self.sink.data, cpu_dw//8)) ] if messages_per_dw > 1: for i in range(dw//8): @@ -207,7 +194,7 @@ class DMAWriter(Module, AutoCSR): class Analyzer(Module, AutoCSR): - def __init__(self, tsc, cri, membus, fifo_depth=128): + def __init__(self, tsc, cri, membus, fifo_depth=128, cpu_dw=32): # shutdown procedure: set enable to 0, wait until busy=0 self.enable = CSRStorage() self.busy = CSRStatus() @@ -219,7 +206,7 @@ class Analyzer(Module, AutoCSR): self.submodules.converter = stream.Converter( message_len, len(membus.dat_w), reverse=True, report_valid_token_count=True) - self.submodules.dma = DMAWriter(membus) + self.submodules.dma = DMAWriter(membus, cpu_dw) enable_r = Signal() self.sync += [ diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py index 84f79dfa8..f81559dde 100644 --- a/artiq/gateware/rtio/dma.py +++ b/artiq/gateware/rtio/dma.py @@ -11,28 +11,20 @@ def _reverse_bytes(s, g): return Cat(reversed(list(s[i*g:(i+1)*g] for i in range(len(s)//g)))) -def reverse_bytes(s): - n = (len(s) + 7)//8 - return Cat(*[s[i*8:min((i + 1)*8, len(s))] - for i in reversed(range(n))]) - - -def convert_signal(signal): +def convert_signal(signal, granularity): assert len(signal) % 8 == 0 nbytes = len(signal)//8 - assert nbytes % 4 == 0 - nwords = nbytes//4 + assert nbytes % granularity == 0 + nwords = nbytes//granularity signal_words = [] for i in range(nwords): - signal_bytes = [] - for j in range(4): - signal_bytes.append(signal[8*(j+i*4):8*((j+i*4)+1)]) - signal_words.extend(reversed(signal_bytes)) - return Cat(*signal_words) + signal_words.append(_reverse_bytes( + signal[i*granularity*8:(i+1)*granularity*8], 8)) + return Cat(signal_words) class WishboneReader(Module): - def __init__(self, bus): + def __init__(self, bus, cpu_dw): self.bus = bus aw = len(bus.adr) @@ -57,18 +49,18 @@ class WishboneReader(Module): If(self.source.ack, data_reg_loaded.eq(0)), If(bus.ack, data_reg_loaded.eq(1), - self.source.data.eq(convert_signal(bus.dat_r)), + self.source.data.eq(convert_signal(bus.dat_r, cpu_dw//8)), self.source.eop.eq(self.sink.eop) ) ] class DMAReader(Module, AutoCSR): - def __init__(self, membus, enable): + def __init__(self, membus, enable, cpu_dw): aw = len(membus.adr) data_alignment = log2_int(len(membus.dat_w)//8) - self.submodules.wb_reader = WishboneReader(membus) + self.submodules.wb_reader = WishboneReader(membus, cpu_dw) self.source = self.wb_reader.source # All numbers in bytes @@ -344,11 +336,11 @@ class CRIMaster(Module, AutoCSR): class DMA(Module): - def __init__(self, membus): + def __init__(self, membus, cpu_dw): self.enable = CSR() flow_enable = Signal() - self.submodules.dma = DMAReader(membus, flow_enable) + self.submodules.dma = DMAReader(membus, flow_enable, cpu_dw) self.submodules.slicer = RecordSlicer(len(membus.dat_w)) self.submodules.time_offset = TimeOffset() self.submodules.cri_master = CRIMaster() From c6e0e264406d647d4fa5210056394bb6b0d713a1 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:29:15 +0800 Subject: [PATCH 02/22] drtio: accept 32b/64b bus --- artiq/gateware/drtio/aux_controller.py | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/artiq/gateware/drtio/aux_controller.py b/artiq/gateware/drtio/aux_controller.py index 8effda67d..051a03a20 100644 --- a/artiq/gateware/drtio/aux_controller.py +++ b/artiq/gateware/drtio/aux_controller.py @@ -212,14 +212,15 @@ class Receiver(Module, AutoCSR): # TODO: FullMemoryWE should be applied by migen.build @FullMemoryWE() class DRTIOAuxController(Module): - def __init__(self, link_layer): - self.bus = wishbone.Interface() + def __init__(self, link_layer, dw=32): + wsb = log2_int(dw//8) + + self.bus = wishbone.Interface(data_width=dw, adr_width=32-wsb) self.submodules.transmitter = Transmitter(link_layer, len(self.bus.dat_w)) self.submodules.receiver = Receiver(link_layer, len(self.bus.dat_w)) - tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False) - rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True) - wsb = log2_int(len(self.bus.dat_w)//8) + tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False, data_width=dw) + rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True, data_width=dw) decoder = wishbone.Decoder(self.bus, [(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus), (lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus)], From dd68b4ab82a9ec1c5badd5db9913d0fecd1e067b Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:30:09 +0800 Subject: [PATCH 03/22] mailbox: parametrize address width --- artiq/gateware/amp/mailbox.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/amp/mailbox.py b/artiq/gateware/amp/mailbox.py index 7c60056d1..6c498b821 100644 --- a/artiq/gateware/amp/mailbox.py +++ b/artiq/gateware/amp/mailbox.py @@ -3,9 +3,9 @@ from misoc.interconnect import wishbone class Mailbox(Module): - def __init__(self, size=1): - self.i1 = wishbone.Interface() - self.i2 = wishbone.Interface() + def __init__(self, size=1, adr_width=30): + self.i1 = wishbone.Interface(data_width=32, adr_width=adr_width) + self.i2 = wishbone.Interface(data_width=32, adr_width=adr_width) # # # From d84ad0095b0688f7164cb6a79f4fc3c918de28be Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:36:36 +0800 Subject: [PATCH 04/22] comm_cpu: select 64b bus if not kasli v1.x --- artiq/gateware/targets/kasli.py | 24 +++++++++++++++++++++--- artiq/gateware/targets/kc705.py | 3 +++ artiq/gateware/targets/metlino.py | 1 + artiq/gateware/targets/sayma_amc.py | 1 + artiq/gateware/targets/sayma_rtm.py | 1 + 5 files changed, 27 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index d47b583b1..5cba517a7 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -104,9 +104,15 @@ class StandaloneBase(MiniSoC, AMPSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, gateware_identifier_str=None, **kwargs): + def __init__(self, gateware_identifier_str=None, hw_rev="v2.0", **kwargs): + if hw_rev in ("v1.0", "v1.1"): + cpu_bus_width = 32 + else: + cpu_bus_width = 64 MiniSoC.__init__(self, cpu_type="vexriscv", + hw_rev=hw_rev, + cpu_bus_width=cpu_bus_width, sdram_controller_type="minicon", l2_size=128*1024, integrated_sram_size=8192, @@ -255,9 +261,15 @@ class MasterBase(MiniSoC, AMPSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, **kwargs): + def __init__(self, rtio_clk_freq=125e6, enable_sata=False, gateware_identifier_str=None, hw_rev="v2.0", **kwargs): + if hw_rev in ("v1.0", "v1.1"): + cpu_bus_width = 32 + else: + cpu_bus_width = 64 MiniSoC.__init__(self, cpu_type="vexriscv", + hw_rev=hw_rev, + cpu_bus_width=cpu_bus_width, sdram_controller_type="minicon", l2_size=128*1024, integrated_sram_size=8192, @@ -431,9 +443,15 @@ class SatelliteBase(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, **kwargs): + def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, gateware_identifier_str=None, hw_rev="v2.0", **kwargs): + if hw_rev in ("v1.0", "v1.1"): + cpu_bus_width = 32 + else: + cpu_bus_width = 64 BaseSoC.__init__(self, cpu_type="vexriscv", + hw_rev=hw_rev, + cpu_bus_width=cpu_bus_width, sdram_controller_type="minicon", l2_size=128*1024, **kwargs) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 2a6e31d6f..6e1fdd1d4 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -132,6 +132,7 @@ class _StandaloneBase(MiniSoC, AMPSoC): def __init__(self, gateware_identifier_str=None, **kwargs): MiniSoC.__init__(self, cpu_type="vexriscv", + cpu_bus_width=64, sdram_controller_type="minicon", l2_size=128*1024, integrated_sram_size=8192, @@ -209,6 +210,7 @@ class _MasterBase(MiniSoC, AMPSoC): def __init__(self, gateware_identifier_str=None, **kwargs): MiniSoC.__init__(self, cpu_type="vexriscv", + cpu_bus_width=64, sdram_controller_type="minicon", l2_size=128*1024, integrated_sram_size=8192, @@ -342,6 +344,7 @@ class _SatelliteBase(BaseSoC): def __init__(self, gateware_identifier_str=None, sma_as_sat=False, **kwargs): BaseSoC.__init__(self, cpu_type="vexriscv", + cpu_bus_width=64, sdram_controller_type="minicon", l2_size=128*1024, integrated_sram_size=8192, diff --git a/artiq/gateware/targets/metlino.py b/artiq/gateware/targets/metlino.py index 74c2e35f0..107dbc78d 100755 --- a/artiq/gateware/targets/metlino.py +++ b/artiq/gateware/targets/metlino.py @@ -43,6 +43,7 @@ class Master(MiniSoC, AMPSoC): def __init__(self, gateware_identifier_str=None, **kwargs): MiniSoC.__init__(self, cpu_type="vexriscv", + cpu_bus_width=64, sdram_controller_type="minicon", l2_size=128*1024, integrated_sram_size=8192, diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 6155eb31f..32ebc8521 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -57,6 +57,7 @@ class SatelliteBase(MiniSoC): def __init__(self, rtio_clk_freq=125e6, identifier_suffix="", gateware_identifier_str=None, with_sfp=False, *, with_wrpll, **kwargs): MiniSoC.__init__(self, cpu_type="vexriscv", + cpu_bus_width=64, sdram_controller_type="minicon", l2_size=128*1024, integrated_sram_size=8192, diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index 7fa740381..a132601d6 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -37,6 +37,7 @@ class _SatelliteBase(BaseSoC): def __init__(self, rtio_clk_freq, *, with_wrpll, gateware_identifier_str, **kwargs): BaseSoC.__init__(self, cpu_type="vexriscv", + cpu_bus_width=64, **kwargs) add_identifier(self, gateware_identifier_str=gateware_identifier_str) self.rtio_clk_freq = rtio_clk_freq From 90f944481c5cb8efebcc235e27e334e15299c220 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:37:36 +0800 Subject: [PATCH 05/22] kernel_cpu: add fpu if not kasli v1.x --- artiq/gateware/amp/kernel_cpu.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/amp/kernel_cpu.py b/artiq/gateware/amp/kernel_cpu.py index a770b4326..bea786be9 100644 --- a/artiq/gateware/amp/kernel_cpu.py +++ b/artiq/gateware/amp/kernel_cpu.py @@ -22,10 +22,10 @@ class KernelCPU(Module): self.cd_sys_kernel.clk.eq(ClockSignal()), self.cd_sys_kernel.rst.eq(self._reset.storage) ] + kasli_v1 = isinstance(platform, kasli.Platform) and platform.hw_rev in ("v1.0", "v1.1") self.submodules.cpu = ClockDomainsRenamer("sys_kernel")( - vexriscv.VexRiscv( - platform, - exec_address)) + vexriscv.VexRiscv(platform, exec_address, + variant="VexRiscv_IMA" if kasli_v1 else "VexRiscv_G")) # DRAM access self.wb_sdram = wishbone.Interface() From cb247f235f552053323ec62d8256c84d3cd49bb9 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:42:05 +0800 Subject: [PATCH 06/22] gateware: pass adr_w/data_w to submodules --- artiq/gateware/amp/kernel_cpu.py | 10 ++++++---- artiq/gateware/amp/soc.py | 16 ++++++++++------ artiq/gateware/targets/kasli.py | 12 ++++++------ artiq/gateware/targets/kc705.py | 10 +++++----- artiq/gateware/targets/metlino.py | 4 ++-- artiq/gateware/targets/sayma_amc.py | 2 +- artiq/gateware/targets/sayma_rtm.py | 2 +- 7 files changed, 31 insertions(+), 25 deletions(-) diff --git a/artiq/gateware/amp/kernel_cpu.py b/artiq/gateware/amp/kernel_cpu.py index bea786be9..6979b7b4f 100644 --- a/artiq/gateware/amp/kernel_cpu.py +++ b/artiq/gateware/amp/kernel_cpu.py @@ -1,4 +1,5 @@ from migen import * +from migen.build.platforms.sinara import kasli from misoc.interconnect.csr import * from misoc.interconnect import wishbone from misoc.cores import vexriscv @@ -14,8 +15,6 @@ class KernelCPU(Module): # # # - self._wb_slaves = WishboneSlaveManager(0x80000000) - # CPU core self.clock_domains.cd_sys_kernel = ClockDomain() self.comb += [ @@ -26,9 +25,12 @@ class KernelCPU(Module): self.submodules.cpu = ClockDomainsRenamer("sys_kernel")( vexriscv.VexRiscv(platform, exec_address, variant="VexRiscv_IMA" if kasli_v1 else "VexRiscv_G")) + + self.cpu_dw = len(self.cpu.dbus.dat_w) + self._wb_slaves = WishboneSlaveManager(0x80000000, dw=self.cpu_dw) # DRAM access - self.wb_sdram = wishbone.Interface() + self.wb_sdram = wishbone.Interface(data_width=self.cpu_dw, adr_width=32-log2_int(self.cpu_dw//8)) self.add_wb_slave(main_mem_origin, 0x10000000, self.wb_sdram) def get_csrs(self): @@ -37,7 +39,7 @@ class KernelCPU(Module): def do_finalize(self): self.submodules.wishbonecon = wishbone.InterconnectShared( [self.cpu.ibus, self.cpu.dbus], - self._wb_slaves.get_interconnect_slaves(), register=True) + self._wb_slaves.get_interconnect_slaves(), register=True, dw=self.cpu_dw) def add_wb_slave(self, origin, length, interface): if self.finalized: diff --git a/artiq/gateware/amp/soc.py b/artiq/gateware/amp/soc.py index 76d79807c..91b75ca3a 100644 --- a/artiq/gateware/amp/soc.py +++ b/artiq/gateware/amp/soc.py @@ -1,3 +1,4 @@ +from migen import * from misoc.cores import timer from misoc.interconnect import wishbone @@ -19,21 +20,24 @@ class AMPSoC: self.csr_devices.append("kernel_cpu") mailbox_size = 3 - self.submodules.mailbox = Mailbox(mailbox_size) - self.add_wb_slave(self.mem_map["mailbox"], 4*mailbox_size, + self.csr_separation = self.kernel_cpu.cpu_dw//8 + + self.submodules.mailbox = Mailbox(mailbox_size, adr_width=32-log2_int(self.csr_separation)) + self.add_wb_slave(self.mem_map["mailbox"], self.csr_separation*mailbox_size, self.mailbox.i1) - self.kernel_cpu.add_wb_slave(self.mem_map["mailbox"], 4*mailbox_size, + self.kernel_cpu.add_wb_slave(self.mem_map["mailbox"], self.csr_separation*mailbox_size, self.mailbox.i2) self.add_memory_region("mailbox", self.mem_map["mailbox"] | 0x80000000, - 4*mailbox_size) + self.csr_separation*mailbox_size) def register_kernel_cpu_csrdevice(self, name, csrs=None): if csrs is None: csrs = getattr(self, name).get_csrs() - bank = wishbone.CSRBank(csrs) + csr_bus = wishbone.Interface(data_width=32, adr_width=32-log2_int(self.csr_separation)) + bank = wishbone.CSRBank(csrs, bus=csr_bus) self.submodules += bank - self.kernel_cpu.add_wb_slave(self.mem_map[name], 4*2**bank.decode_bits, bank.bus) + self.kernel_cpu.add_wb_slave(self.mem_map[name], self.csr_separation*2**bank.decode_bits, bank.bus) self.add_csr_region(name, self.mem_map[name] | 0x80000000, 32, csrs) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 5cba517a7..311028fcb 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -144,7 +144,7 @@ class StandaloneBase(MiniSoC, AMPSoC): self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - rtio.DMA(self.get_native_sdram_if())) + rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( @@ -162,7 +162,7 @@ class StandaloneBase(MiniSoC, AMPSoC): self.rtio_crg.cd_rtio.clk) self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri, - self.get_native_sdram_if()) + self.get_native_sdram_if(), cpu_dw=self.cpu_dw) self.csr_devices.append("rtio_analyzer") @@ -345,7 +345,7 @@ class MasterBase(MiniSoC, AMPSoC): self.drtio_cri.append(core.cri) self.csr_devices.append(core_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) @@ -386,7 +386,7 @@ class MasterBase(MiniSoC, AMPSoC): self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - rtio.DMA(self.get_native_sdram_if())) + rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( @@ -398,7 +398,7 @@ class MasterBase(MiniSoC, AMPSoC): self.csr_devices.append("routing_table") self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave, - self.get_native_sdram_if()) + self.get_native_sdram_if(), cpu_dw=self.cpu_dw) self.csr_devices.append("rtio_analyzer") # Never running out of stupid features, GTs on A7 make you pack @@ -539,7 +539,7 @@ class SatelliteBase(BaseSoC): self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 6e1fdd1d4..4cec96e87 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -177,7 +177,7 @@ class _StandaloneBase(MiniSoC, AMPSoC): self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - rtio.DMA(self.get_native_sdram_if())) + rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( @@ -193,7 +193,7 @@ class _StandaloneBase(MiniSoC, AMPSoC): self.rtio_crg.cd_rtio.clk) self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri, - self.get_native_sdram_if()) + self.get_native_sdram_if(), cpu_dw=self.cpu_dw) self.csr_devices.append("rtio_analyzer") @@ -265,7 +265,7 @@ class _MasterBase(MiniSoC, AMPSoC): self.drtio_cri.append(core.cri) self.csr_devices.append(core_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) @@ -323,7 +323,7 @@ class _MasterBase(MiniSoC, AMPSoC): self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - rtio.DMA(self.get_native_sdram_if())) + rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( @@ -407,7 +407,7 @@ class _SatelliteBase(BaseSoC): self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) diff --git a/artiq/gateware/targets/metlino.py b/artiq/gateware/targets/metlino.py index 107dbc78d..ffb2b38b9 100755 --- a/artiq/gateware/targets/metlino.py +++ b/artiq/gateware/targets/metlino.py @@ -97,7 +97,7 @@ class Master(MiniSoC, AMPSoC): drtio_cri.append(core.cri) self.csr_devices.append(core_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) @@ -150,7 +150,7 @@ class Master(MiniSoC, AMPSoC): self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc) self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - rtio.DMA(self.get_native_sdram_if())) + rtio.DMA(self.get_native_sdram_if(), self.cpu_dw)) self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 32ebc8521..527d37b5c 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -118,7 +118,7 @@ class SatelliteBase(MiniSoC): self.drtio_cri.append(core.cri) self.csr_devices.append(corerep_name) - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) setattr(self.submodules, coreaux_name, coreaux) self.csr_devices.append(coreaux_name) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index a132601d6..9d8a818b4 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -80,7 +80,7 @@ class _SatelliteBase(BaseSoC): self.submodules.drtiosat = core self.csr_devices.append("drtiosat") - coreaux = cdr(DRTIOAuxController(core.link_layer)) + coreaux = cdr(DRTIOAuxController(core.link_layer, self.cpu_dw)) self.submodules.drtioaux0 = coreaux self.csr_devices.append("drtioaux0") From 0898e101e25f451a1dff8a714c2b7df37a8ae30c Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:51:50 +0800 Subject: [PATCH 07/22] board_misoc: reuse riscv dir for comm & kernel --- artiq/firmware/libboard_misoc/build.rs | 9 +++------ artiq/firmware/libboard_misoc/lib.rs | 2 +- .../libboard_misoc/{riscv32ima => riscv32}/boot.rs | 0 .../libboard_misoc/{riscv32ima => riscv32}/cache.rs | 0 .../libboard_misoc/{riscv32ima => riscv32}/mod.rs | 0 .../libboard_misoc/{riscv32ima => riscv32}/pmp.rs | 0 .../libboard_misoc/{riscv32ima => riscv32}/vectors.S | 0 7 files changed, 4 insertions(+), 7 deletions(-) rename artiq/firmware/libboard_misoc/{riscv32ima => riscv32}/boot.rs (100%) rename artiq/firmware/libboard_misoc/{riscv32ima => riscv32}/cache.rs (100%) rename artiq/firmware/libboard_misoc/{riscv32ima => riscv32}/mod.rs (100%) rename artiq/firmware/libboard_misoc/{riscv32ima => riscv32}/pmp.rs (100%) rename artiq/firmware/libboard_misoc/{riscv32ima => riscv32}/vectors.S (100%) diff --git a/artiq/firmware/libboard_misoc/build.rs b/artiq/firmware/libboard_misoc/build.rs index 8160db88a..11d5aac2f 100644 --- a/artiq/firmware/libboard_misoc/build.rs +++ b/artiq/firmware/libboard_misoc/build.rs @@ -1,19 +1,16 @@ extern crate build_misoc; extern crate cc; -use std::env; use std::path::Path; fn main() { build_misoc::cfg(); - let triple = env::var("TARGET").unwrap(); - let arch = triple.split("-").next().unwrap(); - let vectors_path = Path::new(arch).join("vectors.S"); + let vectors_path = "riscv32/vectors.S"; - println!("cargo:rerun-if-changed={}", vectors_path.to_str().unwrap()); + println!("cargo:rerun-if-changed={}", vectors_path); cc::Build::new() .flag("--target=riscv32-unknown-elf") - .file(vectors_path) + .file(Path::new(vectors_path)) .compile("vectors"); } diff --git a/artiq/firmware/libboard_misoc/lib.rs b/artiq/firmware/libboard_misoc/lib.rs index 729f4d63b..3189ccfcd 100644 --- a/artiq/firmware/libboard_misoc/lib.rs +++ b/artiq/firmware/libboard_misoc/lib.rs @@ -8,7 +8,7 @@ extern crate log; extern crate smoltcp; #[cfg(target_arch = "riscv32")] -#[path = "riscv32ima/mod.rs"] +#[path = "riscv32/mod.rs"] mod arch; #[cfg(target_arch = "riscv32")] diff --git a/artiq/firmware/libboard_misoc/riscv32ima/boot.rs b/artiq/firmware/libboard_misoc/riscv32/boot.rs similarity index 100% rename from artiq/firmware/libboard_misoc/riscv32ima/boot.rs rename to artiq/firmware/libboard_misoc/riscv32/boot.rs diff --git a/artiq/firmware/libboard_misoc/riscv32ima/cache.rs b/artiq/firmware/libboard_misoc/riscv32/cache.rs similarity index 100% rename from artiq/firmware/libboard_misoc/riscv32ima/cache.rs rename to artiq/firmware/libboard_misoc/riscv32/cache.rs diff --git a/artiq/firmware/libboard_misoc/riscv32ima/mod.rs b/artiq/firmware/libboard_misoc/riscv32/mod.rs similarity index 100% rename from artiq/firmware/libboard_misoc/riscv32ima/mod.rs rename to artiq/firmware/libboard_misoc/riscv32/mod.rs diff --git a/artiq/firmware/libboard_misoc/riscv32ima/pmp.rs b/artiq/firmware/libboard_misoc/riscv32/pmp.rs similarity index 100% rename from artiq/firmware/libboard_misoc/riscv32ima/pmp.rs rename to artiq/firmware/libboard_misoc/riscv32/pmp.rs diff --git a/artiq/firmware/libboard_misoc/riscv32ima/vectors.S b/artiq/firmware/libboard_misoc/riscv32/vectors.S similarity index 100% rename from artiq/firmware/libboard_misoc/riscv32ima/vectors.S rename to artiq/firmware/libboard_misoc/riscv32/vectors.S From b3e315e24af56b609e9a41c882287ed152d1d1f0 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:57:13 +0800 Subject: [PATCH 08/22] rust: find json file using CARGO_TRIPLE --- artiq/firmware/bootloader/Makefile | 2 +- artiq/firmware/ksupport/Makefile | 2 +- artiq/firmware/riscv32g-unknown-none-elf.json | 40 ++++++++++++ .../firmware/riscv32ima-unknown-none-elf.json | 61 +++++++++---------- artiq/firmware/runtime/Makefile | 2 +- artiq/firmware/satman/Makefile | 2 +- 6 files changed, 74 insertions(+), 35 deletions(-) create mode 100644 artiq/firmware/riscv32g-unknown-none-elf.json diff --git a/artiq/firmware/bootloader/Makefile b/artiq/firmware/bootloader/Makefile index 4dbd7b608..82baef3eb 100644 --- a/artiq/firmware/bootloader/Makefile +++ b/artiq/firmware/bootloader/Makefile @@ -11,7 +11,7 @@ all:: bootloader.bin $(RUSTOUT)/libbootloader.a: $(cargo) --target-dir ./cargo \ --manifest-path $(BOOTLOADER_DIRECTORY)/Cargo.toml \ - --target $(BOOTLOADER_DIRECTORY)/../riscv32ima-unknown-none-elf.json + --target $(BOOTLOADER_DIRECTORY)/../$(CARGO_TRIPLE).json bootloader.elf: $(RUSTOUT)/libbootloader.a $(link) -T $(BOOTLOADER_DIRECTORY)/bootloader.ld diff --git a/artiq/firmware/ksupport/Makefile b/artiq/firmware/ksupport/Makefile index f1fbfc19a..b73faea50 100644 --- a/artiq/firmware/ksupport/Makefile +++ b/artiq/firmware/ksupport/Makefile @@ -22,7 +22,7 @@ all:: ksupport.elf $(RUSTOUT)/libksupport.a: $(cargo) --target-dir ./cargo \ --manifest-path $(KSUPPORT_DIRECTORY)/Cargo.toml \ - --target $(KSUPPORT_DIRECTORY)/../riscv32ima-unknown-none-elf.json + --target $(KSUPPORT_DIRECTORY)/../$(CARGO_TRIPLE).json ksupport.elf: $(RUSTOUT)/libksupport.a glue.o $(link) -T $(KSUPPORT_DIRECTORY)/ksupport.ld \ diff --git a/artiq/firmware/riscv32g-unknown-none-elf.json b/artiq/firmware/riscv32g-unknown-none-elf.json new file mode 100644 index 000000000..2a3fb8bfb --- /dev/null +++ b/artiq/firmware/riscv32g-unknown-none-elf.json @@ -0,0 +1,40 @@ +{ + "arch": "riscv32", + "code-model": "medium", + "cpu": "generic-rv32", + "crt-static-respected": true, + "data-layout": "e-m:e-p:32:32-i64:64-n32-S128", + "dynamic-linking": true, + "executables": true, + "features": "+m,+a,+f,+d", + "has-elf-tls": true, + "has-rpath": true, + "llvm-abiname": "ilp32d", + "llvm-target": "riscv32-unknown-linux", + "max-atomic-width": 32, + "position-independent-executables": true, + "pre-link-args": { + "gcc": [ + "-Wl,--as-needed", + "-Wl,-z,noexecstack" + ] + }, + "relro-level": "full", + "target-family": "unix", + "target-pointer-width": "32", + "unsupported-abis": [ + "cdecl", + "stdcall", + "fastcall", + "vectorcall", + "thiscall", + "aapcs", + "win64", + "sysv64", + "ptx-kernel", + "msp430-interrupt", + "x86-interrupt", + "amdgpu-kernel" + ] +} + \ No newline at end of file diff --git a/artiq/firmware/riscv32ima-unknown-none-elf.json b/artiq/firmware/riscv32ima-unknown-none-elf.json index ddacc0247..e41408842 100644 --- a/artiq/firmware/riscv32ima-unknown-none-elf.json +++ b/artiq/firmware/riscv32ima-unknown-none-elf.json @@ -1,32 +1,31 @@ { - "arch": "riscv32", - "cpu": "generic-rv32", - "data-layout": "e-m:e-p:32:32-i64:64-n32-S128", - "eh-frame-header": false, - "emit-debug-gdb-scripts": false, - "executables": true, - "features": "+m,+a,-c", - "is-builtin": false, - "linker": "rust-lld", - "linker-flavor": "ld.lld", - "llvm-target": "riscv32", - "max-atomic-width": 32, - "panic-strategy": "unwind", - "relocation-model": "static", - "target-pointer-width": "32", - "unsupported-abis": [ - "cdecl", - "stdcall", - "fastcall", - "vectorcall", - "thiscall", - "aapcs", - "win64", - "sysv64", - "ptx-kernel", - "msp430-interrupt", - "x86-interrupt", - "amdgpu-kernel" - ] - } - \ No newline at end of file + "arch": "riscv32", + "cpu": "generic-rv32", + "data-layout": "e-m:e-p:32:32-i64:64-n32-S128", + "eh-frame-header": false, + "emit-debug-gdb-scripts": false, + "executables": true, + "features": "+m,+a,-c", + "is-builtin": false, + "linker": "rust-lld", + "linker-flavor": "ld.lld", + "llvm-target": "riscv32", + "max-atomic-width": 32, + "panic-strategy": "unwind", + "relocation-model": "static", + "target-pointer-width": "32", + "unsupported-abis": [ + "cdecl", + "stdcall", + "fastcall", + "vectorcall", + "thiscall", + "aapcs", + "win64", + "sysv64", + "ptx-kernel", + "msp430-interrupt", + "x86-interrupt", + "amdgpu-kernel" + ] +} diff --git a/artiq/firmware/runtime/Makefile b/artiq/firmware/runtime/Makefile index 00506b2f3..3e4b91ba3 100644 --- a/artiq/firmware/runtime/Makefile +++ b/artiq/firmware/runtime/Makefile @@ -18,7 +18,7 @@ all:: runtime.bin runtime.fbi $(RUSTOUT)/libruntime.a: $(cargo) --target-dir ./cargo \ --manifest-path $(RUNTIME_DIRECTORY)/Cargo.toml \ - --target $(RUNTIME_DIRECTORY)/../riscv32ima-unknown-none-elf.json + --target $(RUNTIME_DIRECTORY)/../$(CARGO_TRIPLE).json runtime.elf: $(RUSTOUT)/libruntime.a ksupport_data.o $(link) -T $(RUNTIME_DIRECTORY)/runtime.ld \ diff --git a/artiq/firmware/satman/Makefile b/artiq/firmware/satman/Makefile index 7c3885c87..82e65d730 100644 --- a/artiq/firmware/satman/Makefile +++ b/artiq/firmware/satman/Makefile @@ -13,7 +13,7 @@ all:: satman.bin satman.fbi $(RUSTOUT)/libsatman.a: $(cargo) --target-dir ./cargo \ --manifest-path $(SATMAN_DIRECTORY)/Cargo.toml \ - --target $(SATMAN_DIRECTORY)/../riscv32ima-unknown-none-elf.json + --target $(SATMAN_DIRECTORY)/../$(CARGO_TRIPLE).json satman.elf: $(RUSTOUT)/libsatman.a $(link) -T $(SATMAN_DIRECTORY)/satman.ld From 03b803e7642fd295259f3c4a5312e0b496057599 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:57:30 +0800 Subject: [PATCH 09/22] firmware: adjust csr separation --- artiq/firmware/ksupport/rtio.rs | 6 ++++-- artiq/firmware/libboard_artiq/rpc_queue.rs | 6 +++--- artiq/firmware/libboard_misoc/sdram.rs | 15 +++++++++------ 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/artiq/firmware/ksupport/rtio.rs b/artiq/firmware/ksupport/rtio.rs index 8736e33f5..d9f568f75 100644 --- a/artiq/firmware/ksupport/rtio.rs +++ b/artiq/firmware/ksupport/rtio.rs @@ -23,6 +23,8 @@ mod imp { pub const RTIO_I_STATUS_WAIT_STATUS: u8 = 4; pub const RTIO_I_STATUS_DESTINATION_UNREACHABLE: u8 = 8; + const OFFSET_MULTIPLE: isize = (csr::CONFIG_DATA_WIDTH_BYTES / 4) as isize; + pub extern fn init() { send(&RtioInitRequest); } @@ -47,14 +49,14 @@ mod imp { #[inline(always)] pub unsafe fn rtio_o_data_write(offset: usize, data: u32) { write_volatile( - csr::rtio::O_DATA_ADDR.offset((csr::rtio::O_DATA_SIZE - 1 - offset) as isize), + csr::rtio::O_DATA_ADDR.offset(OFFSET_MULTIPLE*(csr::rtio::O_DATA_SIZE - 1 - offset) as isize), data); } #[inline(always)] pub unsafe fn rtio_i_data_read(offset: usize) -> u32 { read_volatile( - csr::rtio::I_DATA_ADDR.offset((csr::rtio::I_DATA_SIZE - 1 - offset) as isize)) + csr::rtio::I_DATA_ADDR.offset(OFFSET_MULTIPLE*(csr::rtio::I_DATA_SIZE - 1 - offset) as isize)) } #[inline(never)] diff --git a/artiq/firmware/libboard_artiq/rpc_queue.rs b/artiq/firmware/libboard_artiq/rpc_queue.rs index 0e2049c81..877ed8c89 100644 --- a/artiq/firmware/libboard_artiq/rpc_queue.rs +++ b/artiq/firmware/libboard_artiq/rpc_queue.rs @@ -1,9 +1,9 @@ use core::ptr::{read_volatile, write_volatile}; use core::slice; -use board_misoc::{mem, cache}; +use board_misoc::{mem, cache, csr::CONFIG_DATA_WIDTH_BYTES}; -const SEND_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 4) as *mut usize; -const RECV_MAILBOX: *mut usize = (mem::MAILBOX_BASE + 8) as *mut usize; +const SEND_MAILBOX: *mut usize = (mem::MAILBOX_BASE + CONFIG_DATA_WIDTH_BYTES as usize) as *mut usize; +const RECV_MAILBOX: *mut usize = (mem::MAILBOX_BASE + (CONFIG_DATA_WIDTH_BYTES * 2) as usize) as *mut usize; const QUEUE_BEGIN: usize = 0x44000000; const QUEUE_END: usize = 0x44ffff80; diff --git a/artiq/firmware/libboard_misoc/sdram.rs b/artiq/firmware/libboard_misoc/sdram.rs index 61951e725..b3e112eb0 100644 --- a/artiq/firmware/libboard_misoc/sdram.rs +++ b/artiq/firmware/libboard_misoc/sdram.rs @@ -2,6 +2,7 @@ mod ddr { use core::{ptr, fmt}; use csr::{dfii, ddrphy}; + use csr::CONFIG_DATA_WIDTH_BYTES; use sdram_phy::{self, spin_cycles}; use sdram_phy::{DFII_COMMAND_CS, DFII_COMMAND_WE, DFII_COMMAND_CAS, DFII_COMMAND_RAS, DFII_COMMAND_WRDATA, DFII_COMMAND_RDDATA}; @@ -14,6 +15,8 @@ mod ddr { const DQS_SIGNAL_COUNT: usize = DFII_PIX_DATA_SIZE / 2; + const CSR_SEPARATION: isize = CONFIG_DATA_WIDTH_BYTES as isize / 4; + macro_rules! log { ($logger:expr, $( $arg:expr ),+) => ( if let &mut Some(ref mut f) = $logger { @@ -46,7 +49,7 @@ mod ddr { for n in 0..DQS_SIGNAL_COUNT { let dq_addr = dfii::PI0_RDDATA_ADDR - .offset((DQS_SIGNAL_COUNT - 1 - n) as isize); + .offset(CSR_SEPARATION * (DQS_SIGNAL_COUNT - 1 - n) as isize); log!(logger, "Module {}:\n", DQS_SIGNAL_COUNT - 1 - n); @@ -100,7 +103,7 @@ mod ddr { let mut failed = false; for n in 0..DQS_SIGNAL_COUNT { let dq_addr = dfii::PI0_RDDATA_ADDR - .offset((DQS_SIGNAL_COUNT - 1 - n) as isize); + .offset(CSR_SEPARATION * (DQS_SIGNAL_COUNT - 1 - n) as isize); delay[n] = 0; high_skew[n] = false; @@ -223,7 +226,7 @@ mod ddr { // Write test pattern for p in 0..DFII_NPHASES { for offset in 0..DFII_PIX_DATA_SIZE { - let addr = DFII_PIX_WRDATA_ADDR[p].offset(offset as isize); + let addr = DFII_PIX_WRDATA_ADDR[p].offset(CSR_SEPARATION * offset as isize); let data = prs[DFII_PIX_DATA_SIZE * p + offset]; ptr::write_volatile(addr, data as u32); } @@ -258,7 +261,7 @@ mod ddr { for p in 0..DFII_NPHASES { for &offset in [n, n + DQS_SIGNAL_COUNT].iter() { - let addr = DFII_PIX_RDDATA_ADDR[p].offset(offset as isize); + let addr = DFII_PIX_RDDATA_ADDR[p].offset(CSR_SEPARATION * offset as isize); let data = prs[DFII_PIX_DATA_SIZE * p + offset]; if ptr::read_volatile(addr) as u8 != data { working = false; @@ -306,7 +309,7 @@ mod ddr { // Write test pattern for p in 0..DFII_NPHASES { for offset in 0..DFII_PIX_DATA_SIZE { - let addr = DFII_PIX_WRDATA_ADDR[p].offset(offset as isize); + let addr = DFII_PIX_WRDATA_ADDR[p].offset(CSR_SEPARATION * offset as isize); let data = prs[DFII_PIX_DATA_SIZE * p + offset]; ptr::write_volatile(addr, data as u32); } @@ -349,7 +352,7 @@ mod ddr { for p in 0..DFII_NPHASES { for &offset in [n, n + DQS_SIGNAL_COUNT].iter() { - let addr = DFII_PIX_RDDATA_ADDR[p].offset(offset as isize); + let addr = DFII_PIX_RDDATA_ADDR[p].offset(CSR_SEPARATION * offset as isize); let data = prs[DFII_PIX_DATA_SIZE * p + offset]; if ptr::read_volatile(addr) as u8 != data { valid = false; From 0d708cd61a83e74ea4c73d95267b999bf26138a3 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 12:59:09 +0800 Subject: [PATCH 10/22] compiler/target: split RISCV target into float/non-float --- artiq/compiler/targets.py | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/artiq/compiler/targets.py b/artiq/compiler/targets.py index e908ce38a..dc5b68be8 100644 --- a/artiq/compiler/targets.py +++ b/artiq/compiler/targets.py @@ -98,7 +98,8 @@ class Target: lltarget = llvm.Target.from_triple(self.triple) llmachine = lltarget.create_target_machine( features=",".join(["+{}".format(f) for f in self.features]), - reloc="pic", codemodel="default") + reloc="pic", codemodel="default", + abiname="ilp32d" if isinstance(self, RV32GTarget) else "") llmachine.set_asm_verbosity(True) return llmachine @@ -252,7 +253,7 @@ class NativeTarget(Target): self.triple = llvm.get_default_triple() host_data_layout = str(llvm.targets.Target.from_default_triple().create_target_machine().target_data) -class RISCVTarget(Target): +class RV32IMATarget(Target): triple = "riscv32-unknown-linux" data_layout = "e-m:e-p:32:32-i64:64-n32-S128" features = ["m", "a"] @@ -264,6 +265,18 @@ class RISCVTarget(Target): tool_addr2line = "llvm-addr2line" tool_cxxfilt = "llvm-cxxfilt" +class RV32GTarget(Target): + triple = "riscv32-unknown-linux" + data_layout = "e-m:e-p:32:32-i64:64-n32-S128" + features = ["m", "a", "f", "d"] + print_function = "core_log" + now_pinning = True + + tool_ld = "ld.lld" + tool_strip = "llvm-strip" + tool_addr2line = "llvm-addr2line" + tool_cxxfilt = "llvm-cxxfilt" + class CortexA9Target(Target): triple = "armv7-unknown-linux-gnueabihf" data_layout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" From 0755757601657785d9ea166eef0d8c8693713fa5 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 13:00:26 +0800 Subject: [PATCH 11/22] compiler/tb: use FPU --- artiq/compiler/testbench/perf.py | 4 ++-- artiq/compiler/testbench/perf_embedding.py | 4 ++-- artiq/compiler/testbench/shlib.py | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/artiq/compiler/testbench/perf.py b/artiq/compiler/testbench/perf.py index 363c88840..2d70bcf84 100644 --- a/artiq/compiler/testbench/perf.py +++ b/artiq/compiler/testbench/perf.py @@ -1,7 +1,7 @@ import sys, os from pythonparser import diagnostic from ..module import Module, Source -from ..targets import RISCVTarget +from ..targets import RV32GTarget from . import benchmark def main(): @@ -30,7 +30,7 @@ def main(): benchmark(lambda: Module(source), "ARTIQ transforms and validators") - benchmark(lambda: RISCVTarget().compile_and_link([module]), + benchmark(lambda: RV32GTarget().compile_and_link([module]), "LLVM optimization and linking") if __name__ == "__main__": diff --git a/artiq/compiler/testbench/perf_embedding.py b/artiq/compiler/testbench/perf_embedding.py index d626d5534..75267cb5b 100644 --- a/artiq/compiler/testbench/perf_embedding.py +++ b/artiq/compiler/testbench/perf_embedding.py @@ -5,7 +5,7 @@ from ...master.databases import DeviceDB, DatasetDB from ...master.worker_db import DeviceManager, DatasetManager from ..module import Module from ..embedding import Stitcher -from ..targets import RISCVTarget +from ..targets import RV32GTarget from . import benchmark @@ -45,7 +45,7 @@ def main(): stitcher = embed() module = Module(stitcher) - target = RISCVTarget() + target = RV32GTarget() llvm_ir = target.compile(module) elf_obj = target.assemble(llvm_ir) elf_shlib = target.link([elf_obj]) diff --git a/artiq/compiler/testbench/shlib.py b/artiq/compiler/testbench/shlib.py index 0aa6386d3..0e2317a5c 100644 --- a/artiq/compiler/testbench/shlib.py +++ b/artiq/compiler/testbench/shlib.py @@ -1,7 +1,7 @@ import sys, os from pythonparser import diagnostic from ..module import Module, Source -from ..targets import RISCVTarget +from ..targets import RV32GTarget def main(): if not len(sys.argv) > 1: @@ -20,7 +20,7 @@ def main(): for filename in sys.argv[1:]: modules.append(Module(Source.from_filename(filename, engine=engine))) - llobj = RISCVTarget().compile_and_link(modules) + llobj = RV32GTarget().compile_and_link(modules) basename, ext = os.path.splitext(sys.argv[-1]) with open(basename + ".so", "wb") as f: From 0f660735bfb85d032277d1a1394d9465cb376250 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 13:02:15 +0800 Subject: [PATCH 12/22] ll_gen: adjust csr address by detecting target class --- .../compiler/transforms/llvm_ir_generator.py | 37 ++++++++++++------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/artiq/compiler/transforms/llvm_ir_generator.py b/artiq/compiler/transforms/llvm_ir_generator.py index 61f66599c..084e5ae09 100644 --- a/artiq/compiler/transforms/llvm_ir_generator.py +++ b/artiq/compiler/transforms/llvm_ir_generator.py @@ -10,6 +10,7 @@ from llvmlite import ir as ll, binding as llvm from ...language import core as language_core from .. import types, builtins, ir from ..embedding import SpecializedFunction +from artiq.compiler.targets import RV32GTarget llvoid = ll.VoidType() @@ -1097,20 +1098,28 @@ class LLVMIRGenerator: if self.target.now_pinning: # Word swap now.old as CPU is little endian # Most significant word is stored in lower address (see generated csr.rs) - llnow_raw = self.llbuilder.load(self.llbuiltin("now"), name=insn.name) - llnow_lo = self.llbuilder.shl(llnow_raw, ll.Constant(lli64, 32)) - llnow_hi = self.llbuilder.lshr(llnow_raw, ll.Constant(lli64, 32)) - return self.llbuilder.or_(llnow_lo, llnow_hi) + csr_offset = 2 if isinstance(self.target, RV32GTarget) else 1 + + llnow_hiptr = self.llbuilder.bitcast(self.llbuiltin("now"), lli32.as_pointer()) + llnow_loptr = self.llbuilder.gep(llnow_hiptr, [self.llindex(csr_offset)]) + llnow_hi = self.llbuilder.load(llnow_hiptr, name="now.hi") + llnow_lo = self.llbuilder.load(llnow_loptr, name="now.lo") + llzext_hi = self.llbuilder.zext(llnow_hi, lli64) + llshifted_hi = self.llbuilder.shl(llzext_hi, ll.Constant(lli64, 32)) + llzext_lo = self.llbuilder.zext(llnow_lo, lli64) + return self.llbuilder.or_(llshifted_hi, llzext_lo) else: return self.llbuilder.call(self.llbuiltin("now_mu"), []) elif insn.op == "at_mu": time, = insn.operands lltime = self.map(time) if self.target.now_pinning: + csr_offset = 2 if isinstance(self.target, RV32GTarget) else 1 + lltime_hi = self.llbuilder.trunc(self.llbuilder.lshr(lltime, ll.Constant(lli64, 32)), lli32) lltime_lo = self.llbuilder.trunc(lltime, lli32) llnow_hiptr = self.llbuilder.bitcast(self.llbuiltin("now"), lli32.as_pointer()) - llnow_loptr = self.llbuilder.gep(llnow_hiptr, [self.llindex(1)]) + llnow_loptr = self.llbuilder.gep(llnow_hiptr, [self.llindex(csr_offset)]) llstore_hi = self.llbuilder.store_atomic(lltime_hi, llnow_hiptr, ordering="seq_cst", align=4) llstore_lo = self.llbuilder.store_atomic(lltime_lo, llnow_loptr, ordering="seq_cst", align=4) return llstore_lo @@ -1120,20 +1129,22 @@ class LLVMIRGenerator: interval, = insn.operands llinterval = self.map(interval) if self.target.now_pinning: - llnowptr = self.llbuiltin("now") - llnow = self.llbuilder.load(llnowptr, name="now.old") - # Word swap now.old as CPU is little endian # Most significant word is stored in lower address (see generated csr.rs) - llnow_lo = self.llbuilder.shl(llnow, ll.Constant(lli64, 32)) - llnow_hi = self.llbuilder.lshr(llnow, ll.Constant(lli64, 32)) - llnow = self.llbuilder.or_(llnow_lo, llnow_hi) + csr_offset = 2 if isinstance(self.target, RV32GTarget) else 1 + + llnow_hiptr = self.llbuilder.bitcast(self.llbuiltin("now"), lli32.as_pointer()) + llnow_loptr = self.llbuilder.gep(llnow_hiptr, [self.llindex(csr_offset)]) + llnow_hi = self.llbuilder.load(llnow_hiptr, name="now.hi") + llnow_lo = self.llbuilder.load(llnow_loptr, name="now.lo") + llzext_hi = self.llbuilder.zext(llnow_hi, lli64) + llshifted_hi = self.llbuilder.shl(llzext_hi, ll.Constant(lli64, 32)) + llzext_lo = self.llbuilder.zext(llnow_lo, lli64) + llnow = self.llbuilder.or_(llshifted_hi, llzext_lo) lladjusted = self.llbuilder.add(llnow, llinterval, name="now.new") lladjusted_hi = self.llbuilder.trunc(self.llbuilder.lshr(lladjusted, ll.Constant(lli64, 32)), lli32) lladjusted_lo = self.llbuilder.trunc(lladjusted, lli32) - llnow_hiptr = self.llbuilder.bitcast(llnowptr, lli32.as_pointer()) - llnow_loptr = self.llbuilder.gep(llnow_hiptr, [self.llindex(1)]) llstore_hi = self.llbuilder.store_atomic(lladjusted_hi, llnow_hiptr, ordering="seq_cst", align=4) llstore_lo = self.llbuilder.store_atomic(lladjusted_lo, llnow_loptr, ordering="seq_cst", align=4) return llstore_lo From 531670d6c5804cad90673b0e7daecf603fd8e275 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 13:03:17 +0800 Subject: [PATCH 13/22] dyld: check ABI --- artiq/firmware/libdyld/elf.rs | 6 ++++++ artiq/firmware/libdyld/lib.rs | 8 +++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/artiq/firmware/libdyld/elf.rs b/artiq/firmware/libdyld/elf.rs index d8712b9fd..a10d9b4c3 100644 --- a/artiq/firmware/libdyld/elf.rs +++ b/artiq/firmware/libdyld/elf.rs @@ -2230,6 +2230,12 @@ pub const R_OR1K_TLS_TPOFF: u8 = 32; pub const R_OR1K_TLS_DTPOFF: u8 = 33; pub const R_OR1K_TLS_DTPMOD: u8 = 34; pub const R_OR1K_NUM: u8 = 35; +pub const EF_RISCV_RVC: u32 = 1; +pub const EF_RISCV_FLOAT_ABI: u32 = 6; +pub const EF_RISCV_FLOAT_ABI_SOFT: u32 = 0; +pub const EF_RISCV_FLOAT_ABI_SINGLE: u32 = 2; +pub const EF_RISCV_FLOAT_ABI_DOUBLE: u32 = 4; +pub const EF_RISCV_FLOAT_ABI_QUAD: u32 = 6; pub const R_RISCV_NONE: u8 = 0; pub const R_RISCV_32: u8 = 1; pub const R_RISCV_64: u8 = 2; diff --git a/artiq/firmware/libdyld/lib.rs b/artiq/firmware/libdyld/lib.rs index 1fec38959..1d89edaee 100644 --- a/artiq/firmware/libdyld/lib.rs +++ b/artiq/firmware/libdyld/lib.rs @@ -219,7 +219,13 @@ impl<'a> Library<'a> { #[cfg(not(target_arch = "riscv32"))] const ARCH: u16 = EM_NONE; - if ehdr.e_ident != IDENT || ehdr.e_type != ET_DYN || ehdr.e_machine != ARCH { + #[cfg(all(target_feature = "f", target_feature = "d"))] + const FLAGS: u32 = EF_RISCV_FLOAT_ABI_DOUBLE; + + #[cfg(not(all(target_feature = "f", target_feature = "d")))] + const FLAGS: u32 = EF_RISCV_FLOAT_ABI_SOFT; + + if ehdr.e_ident != IDENT || ehdr.e_type != ET_DYN || ehdr.e_machine != ARCH || ehdr.e_flags != FLAGS { return Err("not a shared library for current architecture")? } From 750b0ce46d6b74f890c0b750049aafa65e3deb77 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 13:04:48 +0800 Subject: [PATCH 14/22] ddb_temp: select appropriate compiler target --- artiq/coredevice/core.py | 10 ++++++---- artiq/frontend/artiq_ddb_template.py | 14 ++++++++------ 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/artiq/coredevice/core.py b/artiq/coredevice/core.py index dc8207266..529c42f98 100644 --- a/artiq/coredevice/core.py +++ b/artiq/coredevice/core.py @@ -11,7 +11,7 @@ from artiq.language.units import * from artiq.compiler.module import Module from artiq.compiler.embedding import Stitcher -from artiq.compiler.targets import RISCVTarget, CortexA9Target +from artiq.compiler.targets import RV32IMATarget, RV32GTarget, CortexA9Target from artiq.coredevice.comm_kernel import CommKernel, CommKernelDummy # Import for side effects (creating the exception classes). @@ -71,11 +71,13 @@ class Core: "core", "ref_period", "coarse_ref_period", "ref_multiplier", } - def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="riscv"): + def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="rv32g"): self.ref_period = ref_period self.ref_multiplier = ref_multiplier - if target == "riscv": - self.target_cls = RISCVTarget + if target == "rv32g": + self.target_cls = RV32GTarget + elif target == "rv32ima": + self.target_cls = RV32IMATarget elif target == "cortexa9": self.target_cls = CortexA9Target else: diff --git a/artiq/frontend/artiq_ddb_template.py b/artiq/frontend/artiq_ddb_template.py index 4dfba4f93..52408a0d4 100755 --- a/artiq/frontend/artiq_ddb_template.py +++ b/artiq/frontend/artiq_ddb_template.py @@ -11,14 +11,16 @@ from artiq.coredevice import jsondesc def process_header(output, description): - if description["target"] not in ("kasli", "kasli_soc"): + if description["target"] == "kasli": + if description["hw_rev"] in ("v1.0", "v1.1"): + cpu_target = "rv32ima" + else: + cpu_target = "rv32g" + elif description["target"] == "kasli_soc": + cpu_target = "cortexa9" + else: raise NotImplementedError - cpu_target = { - "kasli": "riscv", - "kasli_soc": "cortexa9" - }[description["target"]] - print(textwrap.dedent(""" # Autogenerated for the {variant} variant core_addr = "{core_addr}" From 02119282b8f069c8b1434708999a31f5018aa20f Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 13:05:30 +0800 Subject: [PATCH 15/22] build_soc: build VexRiscv_G if not kasli v1.x --- artiq/build_soc.py | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/artiq/build_soc.py b/artiq/build_soc.py index e3a1f3360..bdf652948 100644 --- a/artiq/build_soc.py +++ b/artiq/build_soc.py @@ -2,6 +2,7 @@ import os import subprocess from migen import * +from migen.build.platforms.sinara import kasli from misoc.interconnect.csr import * from misoc.integration.builder import * @@ -57,11 +58,17 @@ def build_artiq_soc(soc, argdict): builder = Builder(soc, **argdict) builder.software_packages = [] builder.add_software_package("bootloader", os.path.join(firmware_dir, "bootloader")) + is_kasli_v1 = isinstance(soc.platform, kasli.Platform) and soc.platform.hw_rev in ("v1.0", "v1.1") if isinstance(soc, AMPSoC): - builder.add_software_package("libm") - builder.add_software_package("libprintf") - builder.add_software_package("libunwind") - builder.add_software_package("ksupport", os.path.join(firmware_dir, "ksupport")) + kernel_cpu_type = "vexriscv" if is_kasli_v1 else "vexriscv-g" + builder.add_software_package("libm", cpu_type=kernel_cpu_type) + builder.add_software_package("libprintf", cpu_type=kernel_cpu_type) + builder.add_software_package("libunwind", cpu_type=kernel_cpu_type) + builder.add_software_package("ksupport", os.path.join(firmware_dir, "ksupport"), cpu_type=kernel_cpu_type) + # Generate unwinder for soft float target (ARTIQ runtime) + # If the kernel lacks FPU, then the runtime unwinder is already generated + if not is_kasli_v1: + builder.add_software_package("libunwind") builder.add_software_package("runtime", os.path.join(firmware_dir, "runtime")) else: # Assume DRTIO satellite. From 09945ecc4d8b06c9761e46985e7d0ee0a0492cde Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 13:05:55 +0800 Subject: [PATCH 16/22] gateware: fix drtio/dma tests --- .../test/drtio/test_aux_controller.py | 58 +++++++------ artiq/gateware/test/rtio/test_dma.py | 87 ++++++++++++------- 2 files changed, 85 insertions(+), 60 deletions(-) diff --git a/artiq/gateware/test/drtio/test_aux_controller.py b/artiq/gateware/test/drtio/test_aux_controller.py index 64e2e15d7..68c9f3bbd 100644 --- a/artiq/gateware/test/drtio/test_aux_controller.py +++ b/artiq/gateware/test/drtio/test_aux_controller.py @@ -33,63 +33,67 @@ class Loopback(Module): class TB(Module): - def __init__(self, nwords): + def __init__(self, nwords, dw): self.submodules.link_layer = Loopback(nwords) self.submodules.aux_controller = ClockDomainsRenamer( - {"rtio": "sys", "rtio_rx": "sys"})(DRTIOAuxController(self.link_layer)) + {"rtio": "sys", "rtio_rx": "sys"})(DRTIOAuxController(self.link_layer, dw)) class TestAuxController(unittest.TestCase): def test_aux_controller(self): - dut = TB(4) + dut = { + 32: TB(4, 32), + 64: TB(4, 64) + } - def link_init(): + def link_init(dw): for i in range(8): yield - yield dut.link_layer.ready.eq(1) + yield dut[dw].link_layer.ready.eq(1) - def send_packet(packet): + def send_packet(packet, dw): for i, d in enumerate(packet): - yield from dut.aux_controller.bus.write(i, d) - yield from dut.aux_controller.transmitter.aux_tx_length.write(len(packet)*4) - yield from dut.aux_controller.transmitter.aux_tx.write(1) + yield from dut[dw].aux_controller.bus.write(i, d) + yield from dut[dw].aux_controller.transmitter.aux_tx_length.write(len(packet)*dw//8) + yield from dut[dw].aux_controller.transmitter.aux_tx.write(1) yield - while (yield from dut.aux_controller.transmitter.aux_tx.read()): + while (yield from dut[dw].aux_controller.transmitter.aux_tx.read()): yield - def receive_packet(): - while not (yield from dut.aux_controller.receiver.aux_rx_present.read()): + def receive_packet(dw): + while not (yield from dut[dw].aux_controller.receiver.aux_rx_present.read()): yield - length = yield from dut.aux_controller.receiver.aux_rx_length.read() + length = yield from dut[dw].aux_controller.receiver.aux_rx_length.read() r = [] - for i in range(length//4): - r.append((yield from dut.aux_controller.bus.read(256+i))) - yield from dut.aux_controller.receiver.aux_rx_present.write(1) + for i in range(length//(dw//8)): + r.append((yield from dut[dw].aux_controller.bus.read(256+i))) + yield from dut[dw].aux_controller.receiver.aux_rx_present.write(1) return r prng = random.Random(0) - def send_and_check_packet(): - data = [prng.randrange(2**32-1) for _ in range(prng.randrange(1, 16))] - yield from send_packet(data) - received = yield from receive_packet() + def send_and_check_packet(dw): + data = [prng.randrange(2**dw-1) for _ in range(prng.randrange(1, 16))] + yield from send_packet(data, dw) + received = yield from receive_packet(dw) self.assertEqual(data, received) - def sim(): - yield from link_init() + def sim(dw): + yield from link_init(dw) for i in range(8): - yield from send_and_check_packet() + yield from send_and_check_packet(dw) @passive - def rt_traffic(): + def rt_traffic(dw): while True: while prng.randrange(4): yield - yield dut.link_layer.tx_rt_frame.eq(1) + yield dut[dw].link_layer.tx_rt_frame.eq(1) yield while prng.randrange(4): yield - yield dut.link_layer.tx_rt_frame.eq(0) + yield dut[dw].link_layer.tx_rt_frame.eq(0) yield - run_simulation(dut, [sim(), rt_traffic()]) + run_simulation(dut[32], [sim(32), rt_traffic(32)]) + run_simulation(dut[64], [sim(64), rt_traffic(64)]) diff --git a/artiq/gateware/test/rtio/test_dma.py b/artiq/gateware/test/rtio/test_dma.py index 84bc4a3ff..c5d220a9f 100644 --- a/artiq/gateware/test/rtio/test_dma.py +++ b/artiq/gateware/test/rtio/test_dma.py @@ -31,24 +31,25 @@ def encode_record(channel, timestamp, address, data): return encode_n(len(r)+1, 1, 1) + r -def pack(x, size): +def pack(x, size, dw): r = [] for i in range((len(x)+size-1)//size): n = 0 - for j in range(i*size, (i+1)*size): - n <<= 8 + for j in range(i*size//(dw//8), (i+1)*size//(dw//8)): + n <<= dw try: - n |= x[j] + encoded = int.from_bytes(x[j*(dw//8): (j+1)*(dw//8)], "little") + n |= encoded except IndexError: pass r.append(n) return r -def encode_sequence(writes, ws): +def encode_sequence(writes, ws, dw): sequence = [b for write in writes for b in encode_record(*write)] sequence.append(0) - return pack(sequence, ws) + return pack(sequence, ws, dw) def do_dma(dut, address): @@ -84,9 +85,9 @@ prng = random.Random(0) class TB(Module): - def __init__(self, ws): - sequence1 = encode_sequence(test_writes1, ws) - sequence2 = encode_sequence(test_writes2, ws) + def __init__(self, ws, dw): + sequence1 = encode_sequence(test_writes1, ws, dw) + sequence2 = encode_sequence(test_writes2, ws, dw) offset = 512//ws assert len(sequence1) < offset sequence = ( @@ -97,7 +98,7 @@ class TB(Module): bus = wishbone.Interface(ws*8) self.submodules.memory = wishbone.SRAM( 1024, init=sequence, bus=bus) - self.submodules.dut = dma.DMA(bus) + self.submodules.dut = dma.DMA(bus, dw) test_writes_full_stack = [ @@ -109,7 +110,7 @@ test_writes_full_stack = [ class FullStackTB(Module): - def __init__(self, ws): + def __init__(self, ws, dw): self.ttl0 = Signal() self.ttl1 = Signal() @@ -121,12 +122,12 @@ class FullStackTB(Module): rtio.Channel.from_phy(self.phy1) ] - sequence = encode_sequence(test_writes_full_stack, ws) + sequence = encode_sequence(test_writes_full_stack, ws, dw) - bus = wishbone.Interface(ws*8) + bus = wishbone.Interface(ws*8, 32-log2_int(dw//8)) self.submodules.memory = wishbone.SRAM( 256, init=sequence, bus=bus) - self.submodules.dut = dma.DMA(bus) + self.submodules.dut = dma.DMA(bus, dw) self.submodules.tsc = rtio.TSC("async") self.submodules.rtio = rtio.Core(self.tsc, rtio_channels) self.comb += self.dut.cri.connect(self.rtio.cri) @@ -134,16 +135,22 @@ class FullStackTB(Module): class TestDMA(unittest.TestCase): def test_dma_noerror(self): - tb = TB(64) + tb = { + 32: TB(64, 32), + 64: TB(64, 64) + } - def do_writes(): - yield from do_dma(tb.dut, 0) - yield from do_dma(tb.dut, 512) + def do_writes(dw): + yield from do_dma(tb[dw].dut, 0) + yield from do_dma(tb[dw].dut, 512) - received = [] + received = { + 32: [], + 64: [] + } @passive - def rtio_sim(): - dut_cri = tb.dut.cri + def rtio_sim(dw): + dut_cri = tb[dw].dut.cri while True: cmd = yield dut_cri.cmd if cmd == cri.commands["nop"]: @@ -153,7 +160,7 @@ class TestDMA(unittest.TestCase): timestamp = yield dut_cri.o_timestamp address = yield dut_cri.o_address data = yield dut_cri.o_data - received.append((channel, timestamp, address, data)) + received[dw].append((channel, timestamp, address, data)) yield dut_cri.o_status.eq(1) for i in range(prng.randrange(10)): @@ -163,32 +170,46 @@ class TestDMA(unittest.TestCase): self.fail("unexpected RTIO command") yield - run_simulation(tb, [do_writes(), rtio_sim()]) - self.assertEqual(received, test_writes1 + test_writes2) + run_simulation(tb[32], [do_writes(32), rtio_sim(32)]) + self.assertEqual(received[32], test_writes1 + test_writes2) + + run_simulation(tb[64], [do_writes(64), rtio_sim(64)]) + self.assertEqual(received[64], test_writes1 + test_writes2) def test_full_stack(self): - tb = FullStackTB(64) + tb = { + 32: FullStackTB(64, 32), + 64: FullStackTB(64, 64) + } - ttl_changes = [] + ttl_changes = { + 32: [], + 64: [] + } @passive - def monitor(): + def monitor(dw): old_ttl_states = [0, 0] for time in itertools.count(): ttl_states = [ - (yield tb.ttl0), - (yield tb.ttl1) + (yield tb[dw].ttl0), + (yield tb[dw].ttl1) ] for i, (old, new) in enumerate(zip(old_ttl_states, ttl_states)): if new != old: - ttl_changes.append((time, i)) + ttl_changes[dw].append((time, i)) old_ttl_states = ttl_states yield - run_simulation(tb, {"sys": [ - do_dma(tb.dut, 0), monitor(), + run_simulation(tb[32], {"sys": [ + do_dma(tb[32].dut, 0), monitor(32), + (None for _ in range(70)), + ]}, {"sys": 8, "rsys": 8, "rtio": 8, "rio": 8, "rio_phy": 8}) + run_simulation(tb[64], {"sys": [ + do_dma(tb[64].dut, 0), monitor(64), (None for _ in range(70)), ]}, {"sys": 8, "rsys": 8, "rtio": 8, "rio": 8, "rio_phy": 8}) correct_changes = [(timestamp + 11, channel) for channel, timestamp, _, _ in test_writes_full_stack] - self.assertEqual(ttl_changes, correct_changes) + self.assertEqual(ttl_changes[32], correct_changes) + self.assertEqual(ttl_changes[64], correct_changes) From db3e5e83e6c45b3037a3f414b2434993f355b1fe Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 13:14:00 +0800 Subject: [PATCH 17/22] bump misoc --- artiq/firmware/ksupport/Makefile | 2 +- flake.lock | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/artiq/firmware/ksupport/Makefile b/artiq/firmware/ksupport/Makefile index b73faea50..e1e3e48fd 100644 --- a/artiq/firmware/ksupport/Makefile +++ b/artiq/firmware/ksupport/Makefile @@ -26,7 +26,7 @@ $(RUSTOUT)/libksupport.a: ksupport.elf: $(RUSTOUT)/libksupport.a glue.o $(link) -T $(KSUPPORT_DIRECTORY)/ksupport.ld \ - -lunwind-elf -lprintf-float -lm + -lunwind-$(CPU)-elf -lprintf-float -lm %.o: $(KSUPPORT_DIRECTORY)/%.c $(compile) diff --git a/flake.lock b/flake.lock index e9c80a1ad..d2e349045 100644 --- a/flake.lock +++ b/flake.lock @@ -61,11 +61,11 @@ "src-misoc": { "flake": false, "locked": { - "lastModified": 1634799783, - "narHash": "sha256-CbeXsLTwwYBWb5cfrVVYkcQYV207gi9+CQhzfeZbXGc=", + "lastModified": 1636345885, + "narHash": "sha256-+6tqAX+ek+jUU8m59vhhp4QS9UK+D2a6pLD1aFDIWX8=", "ref": "master", - "rev": "855914deace34880c69589022c52a8921f431063", - "revCount": 2375, + "rev": "87f77a739b587a6602b87ee1a94da509d36ba269", + "revCount": 2414, "submodules": true, "type": "git", "url": "https://github.com/m-labs/misoc.git" From ac2f55b3ffca761e6d326e689739ecd8397d4c02 Mon Sep 17 00:00:00 2001 From: occheung Date: Mon, 8 Nov 2021 16:55:29 +0800 Subject: [PATCH 18/22] flake: patch llvmlite --- flake.nix | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/flake.nix b/flake.nix index a43321d0e..fe46d4cd7 100644 --- a/flake.nix +++ b/flake.nix @@ -102,11 +102,18 @@ llvmlite-new = pkgs.python3Packages.buildPythonPackage rec { pname = "llvmlite"; - version = "0.37.0rc2"; + version = "0.37.0-artiq"; src = pkgs.python3Packages.fetchPypi { - inherit pname version; - sha256 = "sha256-F1quz+76JOt1jaQPVzdKe7RfN6gWG2lyE82qTvgyY/c="; + inherit pname; + version = "0.37.0"; + sha256 = "sha256-Y5K4cM0BjsDGRda7uRjWqg7sqMYmdLqu4whi1raGWxU="; }; + patches = [ + (pkgs.fetchurl { + url = "https://git.m-labs.hk/M-Labs/nix-scripts/raw/branch/master/artiq-fast/pkgs/llvmlite-abiname.diff"; + sha256 = "1zlss9vlhjgch6gf5gc0647kkjdwjk0833ld88xwd9vmwvkdmp3v"; + }) + ]; nativeBuildInputs = [ pkgs.llvm_11 ]; # Disable static linking # https://github.com/numba/llvmlite/issues/93 From 80115fcc022400e2f0e914481a1f13dd6d33e70b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 8 Nov 2021 17:34:30 +0800 Subject: [PATCH 19/22] flake: apply llvmlite callsite patch --- flake.nix | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/flake.nix b/flake.nix index fe46d4cd7..4630d3ec8 100644 --- a/flake.nix +++ b/flake.nix @@ -113,6 +113,10 @@ url = "https://git.m-labs.hk/M-Labs/nix-scripts/raw/branch/master/artiq-fast/pkgs/llvmlite-abiname.diff"; sha256 = "1zlss9vlhjgch6gf5gc0647kkjdwjk0833ld88xwd9vmwvkdmp3v"; }) + (pkgs.fetchurl { + url = "https://git.m-labs.hk/M-Labs/nix-scripts/raw/branch/master/artiq-fast/pkgs/llvmlite-callsite.diff"; + sha256 = "sha256-JrIXPnI7E7Y5NIFxswVBmRfQvv61lqKDDnNJrr+nDCg="; + }) ]; nativeBuildInputs = [ pkgs.llvm_11 ]; # Disable static linking From c029977a27fc05b9c49b8865949704184d314622 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 10 Nov 2021 09:54:34 +0800 Subject: [PATCH 20/22] flake: update dependencies --- flake.lock | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/flake.lock b/flake.lock index d2e349045..0c5b07076 100644 --- a/flake.lock +++ b/flake.lock @@ -3,11 +3,11 @@ "mozilla-overlay": { "flake": false, "locked": { - "lastModified": 1629225446, - "narHash": "sha256-HJX4Pc5ZUAg4apxB/XHuJ+6ukzvRQqeZMjscOBst2bA=", + "lastModified": 1636047415, + "narHash": "sha256-iDFogua24bhFJZSxG/jhZbbNxDXuKP9S/pyRIYzrRPM=", "owner": "mozilla", "repo": "nixpkgs-mozilla", - "rev": "0510159186dd2ef46e5464484fbdf119393afa58", + "rev": "cf58c4c67b15b402e77a2665b9e7bad3e9293cb2", "type": "github" }, "original": { @@ -18,11 +18,11 @@ }, "nixpkgs": { "locked": { - "lastModified": 1634758644, - "narHash": "sha256-H3UW/msC6wadg28lcgZv2Ge/P7dWxesL6i37a0GOeyM=", + "lastModified": 1636333654, + "narHash": "sha256-3wh9PtCzcaJQuZrgZ+ygKfhltkDNNqT6zOzGsRbjZEo=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "70904d4a9927a4d6e05c72c4aaac4370e05107f3", + "rev": "e74894146a42ba552ebafa19ab2d1df7ccbc1738", "type": "github" }, "original": { @@ -61,11 +61,11 @@ "src-misoc": { "flake": false, "locked": { - "lastModified": 1636345885, - "narHash": "sha256-+6tqAX+ek+jUU8m59vhhp4QS9UK+D2a6pLD1aFDIWX8=", + "lastModified": 1636508796, + "narHash": "sha256-5dRDFxwKye4X6QQkdNma3SJknPXZDUUyF9GUwgS1Otc=", "ref": "master", - "rev": "87f77a739b587a6602b87ee1a94da509d36ba269", - "revCount": 2414, + "rev": "51ea207bfbc03a552071df0bbf770913ba904217", + "revCount": 2416, "submodules": true, "type": "git", "url": "https://github.com/m-labs/misoc.git" From 46604300a20430c66c58e3c4722e56fc2808c740 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 10 Nov 2021 14:59:02 +0800 Subject: [PATCH 21/22] flake: update dependencies --- flake.lock | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/flake.lock b/flake.lock index 0c5b07076..cfa0d3a4d 100644 --- a/flake.lock +++ b/flake.lock @@ -61,11 +61,11 @@ "src-misoc": { "flake": false, "locked": { - "lastModified": 1636508796, - "narHash": "sha256-5dRDFxwKye4X6QQkdNma3SJknPXZDUUyF9GUwgS1Otc=", + "lastModified": 1636527305, + "narHash": "sha256-/2XTejqj0Bo81HaTrlTSWwInnWwsuqnq+CURXbpIrkA=", "ref": "master", - "rev": "51ea207bfbc03a552071df0bbf770913ba904217", - "revCount": 2416, + "rev": "f5203e406520874e15ab5d070058ef642fc57fd9", + "revCount": 2417, "submodules": true, "type": "git", "url": "https://github.com/m-labs/misoc.git" From f0c50c80e67ee1bca336c8bf6689b554922fde04 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 12 Nov 2021 19:28:51 +0800 Subject: [PATCH 22/22] flake: update dependencies --- flake.lock | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/flake.lock b/flake.lock index cfa0d3a4d..b01ba2a41 100644 --- a/flake.lock +++ b/flake.lock @@ -3,11 +3,11 @@ "mozilla-overlay": { "flake": false, "locked": { - "lastModified": 1636047415, + "lastModified": 1636569584, "narHash": "sha256-iDFogua24bhFJZSxG/jhZbbNxDXuKP9S/pyRIYzrRPM=", "owner": "mozilla", "repo": "nixpkgs-mozilla", - "rev": "cf58c4c67b15b402e77a2665b9e7bad3e9293cb2", + "rev": "9f70f86d73fa97e043bebeb58e5676d157069cfb", "type": "github" }, "original": { @@ -18,11 +18,11 @@ }, "nixpkgs": { "locked": { - "lastModified": 1636333654, - "narHash": "sha256-3wh9PtCzcaJQuZrgZ+ygKfhltkDNNqT6zOzGsRbjZEo=", + "lastModified": 1636552551, + "narHash": "sha256-k7Hq/bvUnRlAfFjPGuw3FsSqqspQdRHsCHpgadw6UkQ=", "owner": "NixOS", "repo": "nixpkgs", - "rev": "e74894146a42ba552ebafa19ab2d1df7ccbc1738", + "rev": "9e86f5f7a19db6da2445f07bafa6694b556f9c6d", "type": "github" }, "original": { @@ -45,11 +45,11 @@ "src-migen": { "flake": false, "locked": { - "lastModified": 1634182166, - "narHash": "sha256-Iw2d8fCgwuuIevkugSqd8Iplj6N+2nR1pn+or5E38Fk=", + "lastModified": 1636715924, + "narHash": "sha256-V3ThFSo2d7OC4SHE0lCkKGQKeFXmvxtwZRWe5NMU3nM=", "owner": "m-labs", "repo": "migen", - "rev": "7507a2bb16dd2cac63535175ce67fb30dfdae1c0", + "rev": "9a0be7a4210ff96043412539eb5388659b81831d", "type": "github" }, "original": {