M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

Bootloader: SDRAM patch for EFC 

- Modification of the CFG flag ensure EFC to initialize DDRPHY correctly
Note that Kasli and EFC share the same model of SDRAM
This commit is contained in:
linuswck 2023-08-01 17:39:21 +08:00 committed by Sébastien Bourdeauducq
parent c206e92f29
commit 758b97426a
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/firmware/libboard_misoc/sdram.rs
View File

@ -217,7 +217,7 @@ mod ddr {
ddrphy::dly_sel_write(1 << (DQS_SIGNAL_COUNT - n - 1)); ddrphy::dly_sel_write(1 << (DQS_SIGNAL_COUNT - n - 1));
ddrphy::rdly_dq_rst_write(1); ddrphy::rdly_dq_rst_write(1);
#[cfg(soc_platform = "kasli")] #[cfg(any(soc_platform = "kasli", soc_platform = "efc"))]
{ {
for _ in 0..3 { for _ in 0..3 {
ddrphy::rdly_dq_bitslip_write(1); ddrphy::rdly_dq_bitslip_write(1);
@ -308,7 +308,7 @@ mod ddr {
let mut max_seen_valid = 0; let mut max_seen_valid = 0;
ddrphy::rdly_dq_rst_write(1); ddrphy::rdly_dq_rst_write(1);
#[cfg(soc_platform = "kasli")] #[cfg(any(soc_platform = "kasli", soc_platform = "efc"))]
{ {
for _ in 0..3 { for _ in 0..3 {
ddrphy::rdly_dq_bitslip_write(1); ddrphy::rdly_dq_bitslip_write(1);
@ -371,7 +371,7 @@ mod ddr {
// Set delay to the middle // Set delay to the middle
ddrphy::rdly_dq_rst_write(1); ddrphy::rdly_dq_rst_write(1);
#[cfg(soc_platform = "kasli")] #[cfg(any(soc_platform = "kasli", soc_platform = "efc"))]
{ {
for _ in 0..3 { for _ in 0..3 {
ddrphy::rdly_dq_bitslip_write(1); ddrphy::rdly_dq_bitslip_write(1);