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urukul: document consequences of incorrect CPLD clock settings

This commit is contained in:
Sebastien Bourdeauducq 2019-06-11 11:12:12 +08:00
parent adf3df2bb5
commit 74e4b01201
1 changed files with 4 additions and 0 deletions
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artiq/coredevice/urukul.py
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@ -154,6 +154,10 @@ class CPLD:
RTIO frequency and the SYNC_IN generator frequency (default: 2 if RTIO frequency and the SYNC_IN generator frequency (default: 2 if
`sync_device` was specified). `sync_device` was specified).
:param core_device: Core device name :param core_device: Core device name
If the clocking is incorrect (for example, setting ``clk_sel`` to the
front panel SMA with no clock connected), then the ``init()`` method of
the DDS channels can fail with the error message ``PLL lock timeout``.
""" """
kernel_invariants = {"refclk", "bus", "core", "io_update", "clk_div"} kernel_invariants = {"refclk", "bus", "core", "io_update", "clk_div"}