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urukul: document consequences of incorrect CPLD clock settings
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@ -154,6 +154,10 @@ class CPLD:
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RTIO frequency and the SYNC_IN generator frequency (default: 2 if
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`sync_device` was specified).
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:param core_device: Core device name
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If the clocking is incorrect (for example, setting ``clk_sel`` to the
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front panel SMA with no clock connected), then the ``init()`` method of
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the DDS channels can fail with the error message ``PLL lock timeout``.
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"""
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kernel_invariants = {"refclk", "bus", "core", "io_update", "clk_div"}
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