M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times

This commit is contained in:
Sebastien Bourdeauducq 2017-06-21 17:01:52 +08:00
parent 66dee9d1ad
commit 74cf074538
3 changed files with 26 additions and 62 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/drtio/transceiver/gtx_7series.py
View File

@ -198,10 +198,6 @@ class GTX_1000BASE_BX10(GTX_20X):
rtio_clk_freq = 62.5e6
class GTX_3G(GTX_20X):
rtio_clk_freq = 150e6
class RXSynchronizer(Module, AutoCSR):
"""Delays the data received in the rtio_rx by a configurable amount
so that it meets s/h in the rtio domain, and recapture it in the rtio

36
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -29,7 +29,7 @@ class Master(MiniSoC, AMPSoC):
}
mem_map.update(MiniSoC.mem_map)
def __init__(self, cfg, **kwargs):
def __init__(self, **kwargs):
MiniSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
@ -45,40 +45,27 @@ class Master(MiniSoC, AMPSoC):
self.comb += platform.request("sfp_tx_disable_n").eq(1)
tx_pads = platform.request("sfp_tx")
rx_pads = platform.request("sfp_rx")
if cfg == "simple_gbe":
# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
# simple TTLs
# 1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
clock_pads=platform.request("sgmii_clock"),
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=self.clk_freq,
clock_div2=True)
elif cfg == "sawg_3g":
# 3Gb link, 150MHz RTIO clock
# with SAWG on local RTIO and AD9154-FMC-EBZ
platform.add_extension(ad9154_fmc_ebz)
self.submodules.transceiver = gtx_7series.GTX_3G(
clock_pads=platform.request("ad9154_refclk"),
tx_pads=tx_pads,
rx_pads=rx_pads,
sys_clk_freq=self.clk_freq)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.config["CONVERTER_SPI_DAC_CS"] = 0
self.config["CONVERTER_SPI_CLK_CS"] = 1
self.config["HAS_AD9516"] = None
else:
raise ValueError
self.submodules.drtio = DRTIOMaster(self.transceiver)
self.csr_devices.append("drtio")
self.add_wb_slave(mem_decoder(self.mem_map["drtio_aux"]),
self.drtio.aux_controller.bus)
self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
platform.add_extension(ad9154_fmc_ebz)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
@ -123,12 +110,9 @@ def main():
description="ARTIQ device binary builder / KC705 DRTIO master")
builder_args(parser)
soc_kc705_args(parser)
parser.add_argument("-c", "--config", default="simple_gbe",
help="configuration: simple_gbe/sawg_3g "
"(default: %(default)s)")
args = parser.parse_args()
soc = Master(args.config, **soc_kc705_argdict(args))
soc = Master(**soc_kc705_argdict(args))
build_artiq_soc(soc, builder_argdict(args))

36
artiq/gateware/targets/kc705_drtio_satellite.py
View File

@ -24,7 +24,7 @@ class Satellite(BaseSoC):
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, cfg, **kwargs):
def __init__(self, **kwargs):
BaseSoC.__init__(self,
cpu_type="or1k",
sdram_controller_type="minicon",
@ -48,28 +48,9 @@ class Satellite(BaseSoC):
self.csr_devices.append("rtio_moninj")
self.comb += platform.request("sfp_tx_disable_n").eq(1)
if cfg == "simple_gbe":
# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
# simple TTLs
transceiver = gtx_7series.GTX_1000BASE_BX10
elif cfg == "sawg_3g":
# 3Gb link, 150MHz RTIO clock
# with SAWG on local RTIO and AD9154-FMC-EBZ
platform.add_extension(ad9154_fmc_ebz)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.config["CONVERTER_SPI_DAC_CS"] = 0
self.config["CONVERTER_SPI_CLK_CS"] = 1
self.config["HAS_AD9516"] = None
transceiver = gtx_7series.GTX_3G
else:
raise ValueError
self.submodules.transceiver = transceiver(
# 1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
clock_pads=platform.request("si5324_clkout"),
tx_pads=platform.request("sfp_tx"),
rx_pads=platform.request("sfp_rx"),
@ -99,6 +80,12 @@ class Satellite(BaseSoC):
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
platform.add_extension(ad9154_fmc_ebz)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
@ -117,12 +104,9 @@ def main():
description="ARTIQ device binary builder / KC705 DRTIO satellite")
builder_args(parser)
soc_kc705_args(parser)
parser.add_argument("-c", "--config", default="simple_gbe",
help="configuration: simple_gbe/sawg_3g "
"(default: %(default)s)")
args = parser.parse_args()
soc = Satellite(args.config, **soc_kc705_argdict(args))
soc = Satellite(**soc_kc705_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.add_software_package("satman", os.path.join(artiq_dir, "firmware", "satman"))
builder.build()