M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 19:28:26 +08:00
Code Issues Projects Releases Wiki Activity

sayma: output a ramp in the absence of SAWG channels

Browse Source
This commit is contained in:
Robert Jördens 2017-12-31 12:18:37 +01:00
parent a371b25525
commit 745e695b09
1 changed files with 30 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
artiq/gateware/targets/sayma_amc_standalone.py
View File

@ -99,6 +99,19 @@ class AD9154(Module, AutoCSR):
self.sync.jesd += conv.eq(Cat(ch.o)) self.sync.jesd += conv.eq(Cat(ch.o))
class AD9154NoSAWG(Module, AutoCSR):
def __init__(self, platform, sys_crg, jesd_crg, dac):
self.submodules.jesd = AD9154JESD(platform, sys_crg, jesd_crg, dac)
self.sawgs = []
for i, conv in enumerate(self.jesd.core.sink.flatten()):
ramp = Signal(16)
self.sync += ramp.eq(ramp + (1 << 9 + i))
self.comb += conv.eq(Cat(ramp
for i in range(len(conv) // len(ramp))))
class Standalone(MiniSoC, AMPSoC): class Standalone(MiniSoC, AMPSoC):
mem_map = { mem_map = {
"cri_con": 0x10000000, "cri_con": 0x10000000,
@ -177,19 +190,23 @@ class Standalone(MiniSoC, AMPSoC):
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
if with_sawg: if with_sawg:
self.submodules.ad9154_crg = AD9154CRG(platform) cls = AD9154
self.submodules.ad9154_0 = AD9154(platform, self.crg, self.ad9154_crg, 0) else:
self.submodules.ad9154_1 = AD9154(platform, self.crg, self.ad9154_crg, 1) cls = AD9154NoSAWG
self.csr_devices.append("ad9154_crg")
self.csr_devices.append("ad9154_0") self.submodules.ad9154_crg = AD9154CRG(platform)
self.csr_devices.append("ad9154_1") self.submodules.ad9154_0 = cls(platform, self.crg, self.ad9154_crg, 0)
self.config["HAS_AD9154"] = None self.submodules.ad9154_1 = cls(platform, self.crg, self.ad9154_crg, 1)
self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"]) self.csr_devices.append("ad9154_crg")
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels) self.csr_devices.append("ad9154_0")
rtio_channels.extend(rtio.Channel.from_phy(phy) self.csr_devices.append("ad9154_1")
for sawg in self.ad9154_0.sawgs + self.config["HAS_AD9154"] = None
self.ad9154_1.sawgs self.add_csr_group("ad9154", ["ad9154_0", "ad9154_1"])
for phy in sawg.phys) self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy)
for sawg in self.ad9154_0.sawgs +
self.ad9154_1.sawgs
for phy in sawg.phys)
self.config["HAS_RTIO_LOG"] = None self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels) self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)