mirror of https://github.com/m-labs/artiq
suservo: documentation, small API changes
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4e2d9abaf7
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73fa572275
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@ -1,4 +1,4 @@
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from artiq.language.core import kernel, delay, portable, now_mu
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from artiq.language.core import kernel, delay, portable, now_mu, delay_mu
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from artiq.language.units import us, ms
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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@ -39,8 +39,18 @@ class SUServo:
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@kernel
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def init(self):
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"""Initialize the Servo, Sampler and both Urukuls.
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Leaves the Servo disabled (see :meth:`set_config`), resets all DDS.
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Urukul initialization is performed blindly as there is no readback from
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the DDS or the CPLDs.
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This method does not alter the profile configuration memory
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or the channel controls.
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"""
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self.set_config(0)
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delay(2*us) # pipeline flush
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delay(3*us) # pipeline flush
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self.pgia.set_config_mu(
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sampler.SPI_CONFIG | spi.SPI_END,
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@ -60,29 +70,62 @@ class SUServo:
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@kernel
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def write(self, addr, value):
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"""Write to Servo memory.
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This method advances the timeline by one coarse RTIO cycle.
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:param addr: Memory location address.
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:param value: Data to be written.
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"""
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rtio_output(now_mu(), self.channel, addr | WE, value)
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delay_mu(self.ref_period_mu)
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@kernel
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def read(self, addr):
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"""Read from Servo memory.
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This method does not advance the timeline but consumes all slack.
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:param addr: Memory location address.
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"""
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rtio_output(now_mu(), self.channel, addr, 0)
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return rtio_input_data(self.channel)
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@kernel
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def set_config(self, start):
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self.write(CONFIG_ADDR, start)
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def set_config(self, enable):
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"""Set SU Servo configuration.
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This method advances the timeline by one Servo memory access.
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:param enable: Enable Servo operation. Disabling takes up to 2 Servo
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cycles (~2.2 µs).
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"""
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self.write(CONFIG_ADDR, enable)
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@kernel
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def get_status(self):
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"""Get current SU Servo status.
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This method does not advance the timeline but consumes all slack.
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:return: Status. Bit 0: enabled, bit 1: done
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"""
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return self.read(CONFIG_ADDR)
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@kernel
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def get_adc_mu(self, adc):
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"""Get an ADC reading (IIR filter input X0).
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This method does not advance the timeline but consumes all slack.
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:param adc: ADC channel number (0-7)
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:return: 16 bit signed Y0
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"""
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return self.read(STATE_SEL | (adc << 1) | (1 << 8))
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@kernel
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def set_gain_mu(self, channel, gain):
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"""Set instrumentation amplifier gain of a channel.
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def set_pgia_mu(self, channel, gain):
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"""Set instrumentation amplifier gain of a ADC channel.
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The four gain settings (0, 1, 2, 3) corresponds to gains of
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(1, 10, 100, 1000) respectively.
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@ -96,6 +139,10 @@ class SUServo:
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self.pgia.write(gains << 16)
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self.gains = gains
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@kernel
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def get_adc(self, adc):
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raise NotImplementedError # FIXME
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class Channel:
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kernel_invariants = {"channel", "core", "servo", "servo_channel"}
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@ -105,28 +152,123 @@ class Channel:
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self.core = dmgr.get(core_device)
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self.servo = dmgr.get(servo_device)
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self.channel = channel
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self.servo_channel = self.channel + 8 - self.servo.channel # FIXME
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# FIXME: this assumes the mem channel is right after the control
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# channels
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self.servo_channel = self.channel + 8 - self.servo.channel
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@kernel
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def set(self, en_out, en_iir=0, profile=0):
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"""Operate channel.
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This method does not advance the timeline.
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:param en_out: RF switch enable
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:param en_iir: IIR updates enable
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:param profile: Active profile (0-31)
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"""
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rtio_output(now_mu(), self.channel, 0,
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en_out | (en_iir << 1) | (profile << 2))
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@kernel
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def set_profile_mu(self, profile, ftw, adc, offset,
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a1, b0, b1, delay, pow=0):
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def set_dds_mu(self, profile, ftw, offset, pow=0):
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"""Set profile DDS coefficients.
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This method advances the timeline by four Servo memory accesses.
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:param profile: Profile number (0-31)
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:param ftw: Frequency tuning word (32 bit unsigned)
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:param offset: IIR offset (setpoint)
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:param pow: Phase offset word (16 bit unsigned)
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"""
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base = (self.servo_channel << 8) | (profile << 3)
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data = [ftw >> 16, b1, pow, adc | (delay << 8), offset, a1, ftw, b0]
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for i in range(8):
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self.servo.write(base + i, data[i])
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self.servo.write(base + 0, ftw >> 16)
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self.servo.write(base + 6, ftw)
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self.servo.write(base + 4, offset)
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self.servo.write(base + 2, pow)
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@kernel
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def set_dds(self, profile, frequency, offset, phase=0.):
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raise NotImplementedError # FIXME
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@kernel
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def set_iir_mu(self, profile, adc, a1, b0, b1, delay=0):
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"""Set profile IIR coefficients.
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This method advances the timeline by four Servo memory accesses.
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:param profile: Profile number (0-31)
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:param adc: ADC channel to use (0-7)
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:param a1: 18 bit signed A1 coefficient (Y1 coefficient,
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feedback, integrator gain)
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:param b0: 18 bit signed B0 coefficient (recent,
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X0 coefficient, feed forward, proportional gain)
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:param b1: 18 bit signed B1 coefficient (old,
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X1 coefficient, feed forward, proportional gain)
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:param delay: Number of Servo cycles (~1.1 µs each) to suppress
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IIR updates for after either (1) enabling or disabling RF output,
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(2) enabling or disabling IIR updates, or (3) setting the active
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profile number: i.e. after invoking :meth:`set`.
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"""
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base = (self.servo_channel << 8) | (profile << 3)
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self.servo.write(base + 1, b1)
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self.servo.write(base + 3, adc | (delay << 8))
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self.servo.write(base + 5, a1)
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self.servo.write(base + 7, b0)
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@kernel
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def set_iir(self, profile, adc, i_gain, p_gain, delay=0.):
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raise NotImplementedError # FIXME
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@kernel
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def get_profile_mu(self, profile, data):
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"""Retrieve profile data.
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The data is returned in the `data` argument as:
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`[ftw >> 16, b1, pow, adc | (delay << 8), offset, a1, ftw, b0]`.
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This method advances the timeline by 32 µs and consumes all slack.
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:param profile: Profile number (0-31)
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:param data: List of 8 integers to write the profile data into
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"""
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base = (self.servo_channel << 8) | (profile << 3)
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for i in range(8):
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for i in range(len(data)):
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data[i] = self.servo.read(base + i)
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delay(2*us)
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delay(4*us)
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@kernel
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def get_asf_mu(self, profile):
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def get_y_mu(self, profile):
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"""Get a profile's IIR state (filter output, Y0).
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The IIR state is also know as the "integrator", or the DDS amplitude
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scale factor. It is 18 bits wide and unsigned.
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This method does not advance the timeline but consumes all slack.
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:param profile: Profile number (0-31)
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:return: 18 bit unsigned Y0
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"""
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return self.servo.read(STATE_SEL | (self.servo_channel << 5) | profile)
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@kernel
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def get_y(self, profile):
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raise NotImplementedError # FIXME
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@kernel
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def set_y_mu(self, profile, y):
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"""Set a profile's IIR state (filter output, Y0).
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The IIR state is also know as the "integrator", or the DDS amplitude
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scale factor. It is 18 bits wide and unsigned.
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This method advances the timeline by one Servo memory access.
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:param profile: Profile number (0-31)
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:param y: 18 bit unsigned Y0
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"""
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return self.servo.write(
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STATE_SEL | (self.servo_channel << 5) | profile, y)
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@kernel
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def set_y(self, profile, y):
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raise NotImplementedError # FIXME
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@ -24,33 +24,48 @@ class SUServo(EnvExperiment):
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self.suservo0.init()
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delay(1*us)
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self.suservo0.cpld0.set_att_mu(0, 255)
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# ADC PGIA gain
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self.suservo0.set_pgia_mu(0, 0)
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# DDS attenuator
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self.suservo0.cpld0.set_att_mu(0, 64)
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delay(1*us)
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assert self.suservo0.get_status() == 2
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print(self.suservo0.get_status())
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delay(3*ms)
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self.suservo0_ch0.set_profile_mu(
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profile=0, ftw=0x12345667, adc=0, offset=0x10,
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a1=-0x2000, b0=0x1ffff, b1=0, delay=0, pow=0xaa55)
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# set up profile 0 on channel 0
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self.suservo0_ch0.set_y_mu(0, 0)
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self.suservo0_ch0.set_iir_mu(
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profile=0, adc=0, a1=-0x800, b0=0x1000, b1=0, delay=0)
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self.suservo0_ch0.set_dds_mu(
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profile=0, ftw=0x12345667, offset=0x1, pow=0xaa55)
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# enable channel
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self.suservo0_ch0.set(en_out=1, en_iir=1, profile=0)
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delay(10*ms)
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# enable servo iterations
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self.suservo0.set_config(1)
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delay(10*ms)
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# read back profile data
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data = [0] * 8
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self.suservo0_ch0.get_profile_mu(0, data)
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self.p(data)
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delay(10*ms)
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# check servo status
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assert self.suservo0.get_status() == 1
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# reach back ADC data
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print(self.suservo0.get_adc_mu(0))
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delay(10*ms)
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print(self.suservo0.get_adc_mu(1))
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# read out IIR data
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print(self.suservo0_ch0.get_y_mu(0))
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delay(10*ms)
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print(self.suservo0_ch0.get_asf_mu(0))
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delay(10*ms)
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print(self.suservo0_ch0.get_asf_mu(0))
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delay(10*ms)
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print(self.suservo0.get_status())
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# repeatedly clear the IIR state/integrator
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# with the ADC yielding 0's and given the profile configuration,
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# this will lead to a slow ram up of the amplitude over about 200ms
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# followed by saturation and repetition.
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while True:
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self.suservo0_ch0.set_y_mu(0, 0)
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delay(.2*s)
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@kernel
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def led(self):
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@ -132,3 +132,13 @@ DAC/ADC drivers
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.. automodule:: artiq.coredevice.novogorny
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:members:
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Compound drivers
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----------------
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:mod:`artiq.coredevice.suservo` module
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++++++++++++++++++++++++++++++++++++++
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.. automodule:: artiq.coredevice.suservo
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:members:
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