serwb/test: adapt to new version

This commit is contained in:
Florent Kermarrec 2018-04-07 15:09:29 +02:00
parent e15f8aa903
commit 73dbc0b6b6
2 changed files with 26 additions and 32 deletions

View File

@ -11,32 +11,39 @@ from misoc.interconnect.wishbone import SRAM
class FakeInit(Module): class FakeInit(Module):
def __init__(self): def __init__(self):
self.ready = 1 self.ready = Signal(reset=1)
class FakeSerdes(Module): class FakeSerdes(Module):
def __init__(self): def __init__(self):
self.tx_ce = Signal()
self.tx_k = Signal(4) self.tx_k = Signal(4)
self.tx_d = Signal(32) self.tx_d = Signal(32)
self.rx_ce = Signal()
self.rx_k = Signal(4) self.rx_k = Signal(4)
self.rx_d = Signal(32) self.rx_d = Signal(32)
# # #
data_ce = Signal(5, reset=0b00001)
self.sync += data_ce.eq(Cat(data_ce[1:], data_ce[0]))
self.comb += [
self.tx_ce.eq(data_ce[0]),
self.rx_ce.eq(data_ce[0])
]
class FakePHY(Module): class FakePHY(Module):
cd = "sys"
def __init__(self): def __init__(self):
self.init = FakeInit() self.submodules.init = FakeInit()
self.serdes = FakeSerdes() self.submodules.serdes = FakeSerdes()
class DUTScrambler(Module): class DUTScrambler(Module):
def __init__(self): def __init__(self):
self.submodules.scrambler = scrambler.Scrambler(sync_interval=16) self.submodules.scrambler = scrambler.Scrambler(sync_interval=16)
self.submodules.descrambler = scrambler.Descrambler() self.submodules.descrambler = scrambler.Descrambler()
self.comb += [ self.comb += self.scrambler.source.connect(self.descrambler.sink)
self.scrambler.source.connect(self.descrambler.sink),
self.descrambler.source.ack.eq(1)
]
class DUTCore(Module): class DUTCore(Module):
@ -53,8 +60,11 @@ class DUTCore(Module):
# connect phy # connect phy
self.comb += [ self.comb += [
phy_master.serdes.rx_ce.eq(phy_slave.serdes.tx_ce),
phy_master.serdes.rx_k.eq(phy_slave.serdes.tx_k), phy_master.serdes.rx_k.eq(phy_slave.serdes.tx_k),
phy_master.serdes.rx_d.eq(phy_slave.serdes.tx_d), phy_master.serdes.rx_d.eq(phy_slave.serdes.tx_d),
phy_slave.serdes.rx_ce.eq(phy_master.serdes.tx_ce),
phy_slave.serdes.rx_k.eq(phy_master.serdes.tx_k), phy_slave.serdes.rx_k.eq(phy_master.serdes.tx_k),
phy_slave.serdes.rx_d.eq(phy_master.serdes.tx_d) phy_slave.serdes.rx_d.eq(phy_master.serdes.tx_d)
] ]
@ -70,16 +80,21 @@ class DUTCore(Module):
class TestSERWBCore(unittest.TestCase): class TestSERWBCore(unittest.TestCase):
def test_scrambler(self): def test_scrambler(self):
def generator(dut): def generator(dut):
# prepare test
prng = random.Random(42)
i = 0 i = 0
last_data = -1 last_data = -1
# test loop
while i != 256: while i != 256:
# stim # stim
if (yield dut.scrambler.sink.ack): yield dut.scrambler.sink.valid.eq(1)
if (yield dut.scrambler.sink.valid) & (yield dut.scrambler.sink.ready):
i += 1 i += 1
yield dut.scrambler.sink.data.eq(i) yield dut.scrambler.sink.data.eq(i)
# check # check
if (yield dut.descrambler.source.stb): yield dut.descrambler.source.ready.eq(prng.randrange(2))
if (yield dut.descrambler.source.valid) & (yield dut.descrambler.source.ready):
current_data = (yield dut.descrambler.source.data) current_data = (yield dut.descrambler.source.data)
if (current_data != (last_data + 1)): if (current_data != (last_data + 1)):
dut.errors += 1 dut.errors += 1

View File

@ -17,7 +17,6 @@ class SerdesModel(Module):
self.rx_bitslip_value = Signal(6) self.rx_bitslip_value = Signal(6)
self.rx_delay_rst = Signal() self.rx_delay_rst = Signal()
self.rx_delay_inc = Signal() self.rx_delay_inc = Signal()
self.rx_delay_ce = Signal()
self.valid_bitslip = Signal(6) self.valid_bitslip = Signal(6)
self.valid_delays = Signal(taps) self.valid_delays = Signal(taps)
@ -35,7 +34,7 @@ class SerdesModel(Module):
bitslip.eq(self.rx_bitslip_value), bitslip.eq(self.rx_bitslip_value),
If(self.rx_delay_rst, If(self.rx_delay_rst,
delay.eq(0) delay.eq(0)
).Elif(self.rx_delay_inc & self.rx_delay_ce, ).Elif(self.rx_delay_inc,
delay.eq(delay + 1) delay.eq(delay + 1)
) )
] ]
@ -123,16 +122,6 @@ class TestSERWBInit(unittest.TestCase):
run_simulation(dut, generator(self, dut, valid_bitslip, valid_delays, True)) run_simulation(dut, generator(self, dut, valid_bitslip, valid_delays, True))
def test_master_init_failure(self): def test_master_init_failure(self):
# partial window at the beginning
dut = DUTMaster()
valid_bitslip = 2
valid_delays = 0b11000000000000000000000000000000
run_simulation(dut, generator(self, dut, valid_bitslip, valid_delays, False))
# partial window at the end
dut = DUTMaster()
valid_bitslip = 2
valid_delays = 0b00000000000000000000000000000011
run_simulation(dut, generator(self, dut, valid_bitslip, valid_delays, False))
# too small window # too small window
dut = DUTMaster() dut = DUTMaster()
valid_bitslip = 2 valid_bitslip = 2
@ -146,16 +135,6 @@ class TestSERWBInit(unittest.TestCase):
run_simulation(dut, generator(self, dut, valid_bitslip, valid_delays, True)) run_simulation(dut, generator(self, dut, valid_bitslip, valid_delays, True))
def test_slave_init_failure(self): def test_slave_init_failure(self):
# partial window at the beginning
dut = DUTSlave()
valid_bitslip = 2
valid_delays = 0b11000000000000000000000000000000
run_simulation(dut, generator(self, dut, valid_bitslip, valid_delays, False))
# partial window at the end
dut = DUTSlave()
valid_bitslip = 2
valid_delays = 0b00000000000000000000000000000011
run_simulation(dut, generator(self, dut, valid_bitslip, valid_delays, False))
# too small window # too small window
dut = DUTSlave() dut = DUTSlave()
valid_bitslip = 2 valid_bitslip = 2