mirror of https://github.com/m-labs/artiq
doc: various cleanups
parent
cb036a30c7
commit
73d0a84b44
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@ -6,10 +6,9 @@ from artiq.devices import rtio_core
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class DDS(AutoContext):
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"""Core device Direct Digital Synthesis (DDS) driver.
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This driver controls DDS devices managed directly by the core device's
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runtime. It also uses a RTIO channel (through
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:class:`artiq.devices.rtio_core.RTIOOut`) to control a RF switch that
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gates the output of the DDS device.
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Controls DDS devices managed directly by the core device's runtime. It also
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uses a RTIO channel (through :class:`artiq.devices.rtio_core.RTIOOut`) to
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control a RF switch that gates the output of the DDS device.
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:param dds_sysclk: DDS system frequency, used for computing the frequency
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tuning words.
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@ -28,8 +28,8 @@ class _RTIOBase(AutoContext):
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class RTIOOut(_RTIOBase):
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"""RTIO output driver.
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This driver configures the corresponding RTIO channel as output on the core
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device and provides functions to set its level.
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Configures the corresponding RTIO channel as output on the core device and
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provides functions to set its level.
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This driver supports zero-length transition suppression. For example, if
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two pulses are emitted back-to-back with no delay between them, they will
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@ -82,9 +82,9 @@ class RTIOOut(_RTIOBase):
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class RTIOIn(_RTIOBase):
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"""RTIO input driver.
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This driver configures the corresponding RTIO channel as input on the core
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device and provides functions to analyze the incoming signal, with
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real-time gating to prevent overflows.
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Configures the corresponding RTIO channel as input on the core device and
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provides functions to analyze the incoming signal, with real-time gating
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to prevent overflows.
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:param core: core device
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:param channel: channel number
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@ -127,7 +127,7 @@ class AutoContext:
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... self.exp2 = SubExperiment(self, bar=self.bar2)
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... self.exp3 = SubExperiment(self, bar=self.bar2 + self.offset)
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...
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>>> def run():
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... def run():
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... self.exp1.run()
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... self.exp2.run()
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... self.exp3.run()
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@ -4,9 +4,9 @@ ARTIQ documentation
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Contents:
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.. toctree::
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:maxdepth: 2
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:maxdepth: 2
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installing
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tutorial
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core_reference
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drivers_reference
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installing
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tutorial
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core_reference
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drivers_reference
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@ -7,29 +7,30 @@ Preparing the core device FPGA board
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You may skip those steps if the board is already flashed.
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You will need:
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* FPGA vendor tools (e.g. Xilinx ISE or Vivado)
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* OpenRISC GCC/binutils toolchain (or1k-elf-...)
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* Python 3.3+
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* Migen and MiSoC (http://m-labs.hk/gateware.html)
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* FPGA vendor tools (e.g. Xilinx ISE or Vivado)
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* OpenRISC GCC/binutils toolchain (or1k-elf-...)
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* Python 3.3+
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* Migen and MiSoC (http://m-labs.hk/gateware.html)
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After these components are installed, build and flash the bitstream and BIOS by running `from the MiSoC top-level directory`: ::
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$ ./make.py -X /path_to/ARTIQ/soc -t artiq all
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$ ./make.py -X /path_to/ARTIQ/soc -t artiq all
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Then, build and flash the ARTIQ runtime: ::
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$ cd /path_to/ARTIQ/soc/runtime
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$ make flash
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$ cd /path_to/ARTIQ/soc/runtime
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$ make flash
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Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the bitstream that was newly written into the flash): ::
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$ flterm --port /dev/ttyUSB1
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MiSoC BIOS http://m-labs.hk
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[...]
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Booting from flash...
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Loading xxxxx bytes from flash...
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Executing booted program.
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ARTIQ runtime built <date/time>
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$ flterm --port /dev/ttyUSB1
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MiSoC BIOS http://m-labs.hk
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[...]
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Booting from flash...
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Loading xxxxx bytes from flash...
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Executing booted program.
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ARTIQ runtime built <date/time>
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The communication parameters are 115200 8-N-1.
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@ -38,40 +39,39 @@ Installing the host-side software
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The main dependency of ARTIQ is LLVM and its Python bindings (http://llvmpy.org). Currently, this installation is tedious because of the OpenRISC support not being merged upstream LLVM and because of incompatibilities between the versions of LLVM that support OpenRISC and the versions of LLVM that support the Python bindings. ::
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git clone https://github.com/openrisc/llvm-or1k
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cd llvm-or1k
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git checkout b3a48efb2c05ed6cedc5395ae726c6a6573ef3ba
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patch -p1 < /path_to/ARTIQ/patches/llvm/*
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git clone https://github.com/openrisc/llvm-or1k
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cd llvm-or1k
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git checkout b3a48efb2c05ed6cedc5395ae726c6a6573ef3ba
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patch -p1 < /path_to/ARTIQ/patches/llvm/*
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cd tools
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git clone https://github.com/openrisc/clang-or1k clang
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cd clang
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git checkout 02d831c7e7dc1517abed9cc96abdfb937af954eb
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patch -p1 < /path_to/ARTIQ/patches/clang/*
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cd tools
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git clone https://github.com/openrisc/clang-or1k clang
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cd clang
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git checkout 02d831c7e7dc1517abed9cc96abdfb937af954eb
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patch -p1 < /path_to/ARTIQ/patches/clang/*
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cd ../..
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mkdir build && cd build
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../configure --prefix=/usr/local/llvm-or1k
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make ENABLE_OPTIMIZED=1 REQUIRES_RTTI=1
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sudo -E make install ENABLE_OPTIMIZED=1 REQUIRES_RTTI=1
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cd ../..
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mkdir build && cd build
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../configure --prefix=/usr/local/llvm-or1k
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make ENABLE_OPTIMIZED=1 REQUIRES_RTTI=1
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sudo -E make install ENABLE_OPTIMIZED=1 REQUIRES_RTTI=1
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cd ../..
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git clone https://github.com/llvmpy/llvmpy
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cd llvmpy
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git checkout llvm-3.4
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git checkout 7af2f7140391d4f708adf2721e84f23c1b89e97a
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patch -p1 < /path_to/ARTIQ/patches/llvmpy/*
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LLVM_CONFIG_PATH=/usr/local/llvm-or1k/bin/llvm-config sudo -E python setup.py install
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cd ../..
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git clone https://github.com/llvmpy/llvmpy
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cd llvmpy
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git checkout llvm-3.4
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git checkout 7af2f7140391d4f708adf2721e84f23c1b89e97a
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patch -p1 < /path_to/ARTIQ/patches/llvmpy/*
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LLVM_CONFIG_PATH=/usr/local/llvm-or1k/bin/llvm-config sudo -E python setup.py install
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.. note::
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``python`` refers to Python 3. You may need to use the ``python3`` command instead of ``python`` on some distributions.
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``python`` refers to Python 3. You may need to use the ``python3`` command instead of ``python`` on some distributions.
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You may want to use ``checkinstall`` instead of ``make install`` (to register the installation with your package manager) and ``pip3 install --user .`` instead of ``sudo -E python setup.py install``.
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You can then install ARTIQ itself: ::
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cd /path_to/ARTIQ
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sudo python setup.py
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cd /path_to/ARTIQ
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sudo python setup.py
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Alternatively, you can simply add the ARTIQ directory to your ``PYTHONPATH`` environment variable. The advantage of this technique is that you will not need to reinstall ARTIQ when modifying or upgrading it, which is useful during development.
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@ -6,33 +6,33 @@ Connecting to the core device
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As a very first step, we will turn on a LED on the core device. Create a file ``led.py`` containing the following: ::
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from artiq import *
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from artiq.devices import corecom_serial, core, gpio_core
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from artiq import *
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from artiq.devices import corecom_serial, core, gpio_core
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class LED(AutoContext):
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parameters = "led"
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class LED(AutoContext):
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parameters = "led"
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@kernel
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def run(self):
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self.led.set(1)
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@kernel
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def run(self):
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self.led.set(1)
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if __name__ == "__main__":
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with corecom_serial.CoreCom() as com:
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core_driver = core.Core(com)
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led_driver = gpio_core.GPIOOut(core=core_driver, channel=0)
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exp = LED(core=core_driver, led=led_driver)
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exp.run()
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if __name__ == "__main__":
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with corecom_serial.CoreCom() as com:
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core_driver = core.Core(com)
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led_driver = gpio_core.GPIOOut(core=core_driver, channel=0)
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exp = LED(core=core_driver, led=led_driver)
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exp.run()
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The central part of our code is our ``LED`` class, that derives from :class:`artiq.language.core.AutoContext`. ``AutoContext`` is part of the mechanism that attaches device drivers and retrieves parameters according to a database. We are not using the database yet; instead, we import and create the device drivers and establish communication with the core device manually. The ``parameters`` string gives the list of devices (and parameters) that our class needs in order to operate. ``AutoContext`` sets them as object attributes, so our ``led`` parameter becomes accessible as ``self.led``. Finally, the ``@kernel`` decorator tells the system that the ``run`` method must be executed on the core device (instead of the host).
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Run this example with: ::
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python led.py
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python led.py
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The LED of the device should turn on. Congratulations! You have a basic ARTIQ system up and running.
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.. note::
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ARTIQ requires Python 3, and you may need to use the ``python3`` command instead of ``python`` on some distributions.
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ARTIQ requires Python 3, and you may need to use the ``python3`` command instead of ``python`` on some distributions.
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Host/core device interaction
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----------------------------
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@ -41,22 +41,22 @@ A method or function running on the core device (which we call a "kernel") may c
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Modify the code as follows: ::
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def input_led_state():
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return int(input("Enter desired LED state: "))
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def input_led_state():
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return int(input("Enter desired LED state: "))
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class LED(AutoContext):
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parameters = "led"
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class LED(AutoContext):
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parameters = "led"
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@kernel
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def run(self):
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self.led.set(input_led_state())
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@kernel
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def run(self):
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self.led.set(input_led_state())
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You can then turn the LED off and on by entering 0 or 1 at the prompt that appears: ::
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$ python led.py
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Enter desired LED state: 1
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$ python led.py
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Enter desired LED state: 0
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$ python led.py
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Enter desired LED state: 1
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$ python led.py
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Enter desired LED state: 0
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What happens is the ARTIQ compiler notices that the ``input_led_state`` function does not have a ``@kernel`` decorator and thus must be executed on the host. When the core device calls it, it sends a request to the host to execute it. The host displays the prompt, collects user input, and sends the result back to the core device, which sets the LED state accordingly.
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@ -81,24 +81,24 @@ The point of running code on the core device is the ability to meet demanding re
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Create a new file ``rtio.py`` containing the following: ::
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from artiq import *
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from artiq.devices import corecom_serial, core, rtio_core
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from artiq import *
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from artiq.devices import corecom_serial, core, rtio_core
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class Tutorial(AutoContext):
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parameters = "o"
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class Tutorial(AutoContext):
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parameters = "o"
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@kernel
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def run(self):
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for i in range(1000000):
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self.o.pulse(2*us)
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delay(2*us)
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@kernel
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def run(self):
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for i in range(1000000):
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self.o.pulse(2*us)
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delay(2*us)
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if __name__ == "__main__":
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with corecom_serial.CoreCom() as com:
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core_driver = core.Core(com)
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out_driver = rtio_core.RTIOOut(core=core_driver, channel=1)
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exp = Tutorial(core=core_driver, o=out_driver)
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exp.run()
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if __name__ == "__main__":
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with corecom_serial.CoreCom() as com:
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core_driver = core.Core(com)
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out_driver = rtio_core.RTIOOut(core=core_driver, channel=1)
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exp = Tutorial(core=core_driver, o=out_driver)
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exp.run()
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Connect an oscilloscope or logic analyzer to the RTIO channel 1 (pin C11 on the Papilio Pro) and run ``python rtio.py``. Notice that the generated signal's period is precisely 4 microseconds, and that it has a duty cycle of precisely 50%. This is not what you would expect if the delay and the pulse were implemented with CPU-controlled GPIO: overhead from the loop management, function calls, etc. would increase the signal's period, and asymmetry in the overhead would cause duty cycle distortion.
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@ -106,23 +106,23 @@ Instead, inside the core device, output timing is generated by the gateware and
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Try reducing the period of the generated waveform until the CPU cannot keep up with the generation of switching events and the underflow exception is raised. Then try catching it: ::
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from artiq.devices.runtime_exceptions import RTIOUnderflow
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from artiq.devices.runtime_exceptions import RTIOUnderflow
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def print_underflow():
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print("RTIO underflow occured")
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def print_underflow():
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print("RTIO underflow occured")
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class Tutorial(AutoContext):
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parameters = "led o"
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class Tutorial(AutoContext):
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parameters = "led o"
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def run(self):
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self.led.set(0)
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try:
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for i in range(1000000):
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self.o.pulse(...)
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delay(...)
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except RTIOUnderflow:
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self.led.set(1)
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print_underflow()
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def run(self):
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self.led.set(0)
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try:
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for i in range(1000000):
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self.o.pulse(...)
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delay(...)
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except RTIOUnderflow:
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self.led.set(1)
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print_underflow()
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Parallel and sequential blocks
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------------------------------
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@ -131,24 +131,24 @@ It is often necessary that several pulses overlap one another. This can be expre
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Try the following code and observe the generated pulses on a 2-channel oscilloscope or logic analyzer: ::
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for i in range(1000000):
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with parallel:
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self.o1.pulse(2*us)
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self.o2.pulse(4*us)
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delay(4*us)
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for i in range(1000000):
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with parallel:
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self.o1.pulse(2*us)
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self.o2.pulse(4*us)
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delay(4*us)
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If you assign ``o2`` to the RTIO channel 2, the signal will be generated on the pin C10 of the Papilio Pro.
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Within a parallel block, some statements can be made sequential again using a ``with sequential`` construct. Observe the pulses generated by this code: ::
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for i in range(1000000):
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with parallel:
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with sequential:
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self.o1.pulse(2*us)
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delay(1*us)
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self.o1.pulse(1*us)
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self.o2.pulse(4*us)
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delay(4*us)
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for i in range(1000000):
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with parallel:
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with sequential:
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self.o1.pulse(2*us)
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delay(1*us)
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self.o1.pulse(1*us)
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self.o2.pulse(4*us)
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delay(4*us)
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.. warning::
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In its current implementation, ARTIQ only supports those pulse sequences that can be interleaved at compile time into a sequential series of on/off events. Combinations of ``parallel``/``sequential`` blocks that require multithreading (due to the parallel execution of long loops, complex algorithms, or algorithms that depend on external input) will cause the compiler to return an error.
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In its current implementation, ARTIQ only supports those pulse sequences that can be interleaved at compile time into a sequential series of on/off events. Combinations of ``parallel``/``sequential`` blocks that require multithreading (due to the parallel execution of long loops, complex algorithms, or algorithms that depend on external input) will cause the compiler to return an error.
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