mirror of https://github.com/m-labs/artiq.git
transforms.interleaver: determine when inlining is not necessary.
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af43c66149
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@ -25,6 +25,9 @@ def delay_free_subgraph(root, limit):
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return True
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return True
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def is_pure_delay(insn):
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return isinstance(insn, ir.Builtin) and insn.op in ("delay", "delay_mu")
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class Interleaver:
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class Interleaver:
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def __init__(self, engine):
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def __init__(self, engine):
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self.engine = engine
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self.engine = engine
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@ -98,12 +101,24 @@ class Interleaver:
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if target_time_delta > 0:
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if target_time_delta > 0:
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assert isinstance(source_terminator, ir.Delay)
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assert isinstance(source_terminator, ir.Delay)
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if isinstance(old_decomp, ir.Builtin) and \
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if is_pure_delay(old_decomp):
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old_decomp.op in ("delay", "delay_mu"):
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new_decomp_expr = ir.Constant(target_time_delta, builtins.TInt64())
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new_decomp_expr = ir.Constant(target_time_delta, builtins.TInt64())
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new_decomp = ir.Builtin("delay_mu", [new_decomp_expr], builtins.TNone())
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new_decomp = ir.Builtin("delay_mu", [new_decomp_expr], builtins.TNone())
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new_decomp.loc = old_decomp.loc
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new_decomp.loc = old_decomp.loc
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source_terminator.basic_block.insert(source_terminator, new_decomp)
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source_terminator.basic_block.insert(source_terminator, new_decomp)
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else: # It's a call.
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need_to_inline = False
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for other_source_block in filter(lambda block: block != source_block,
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source_blocks):
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other_source_terminator = other_source_block.terminator()
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if not (is_pure_delay(other_source_terminator.decomposition()) and \
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iodelay.is_const(other_source_terminator.expr) and \
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other_source_terminator.expr.fold().value >= source_block_delay):
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need_to_inline = True
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break
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if need_to_inline:
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assert False
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else:
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else:
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old_decomp, new_decomp = None, old_decomp
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old_decomp, new_decomp = None, old_decomp
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