mirror of https://github.com/m-labs/artiq.git
urukul: make RF switch TTL optional
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317c257778
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@ -158,7 +158,7 @@ class AD9910:
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ftw_per_hz: KernelInvariant[float]
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sysclk_per_mu: KernelInvariant[int32]
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sysclk: KernelInvariant[float]
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sw: KernelInvariant[TTLOut]
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sw: KernelInvariant[Option[TTLOut]]
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sync_data: KernelInvariant[SyncDataUser]
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phase_mode: Kernel[int32]
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@ -175,8 +175,9 @@ class AD9910:
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assert 3 <= chip_select <= 7
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self.chip_select = chip_select
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if sw_device:
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self.sw = dmgr.get(sw_device)
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# NAC3TODO: support no sw
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self.sw = Some(dmgr.get(sw_device))
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else:
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self.sw = none
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clk = self.cpld.refclk / [4, 1, 2, 4][self.cpld.clk_div]
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self.pll_en = pll_en
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self.pll_n = pll_n
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@ -1,6 +1,6 @@
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from numpy import int32, int64
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from artiq.language.core import KernelInvariant, nac3, kernel, portable
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from artiq.language.core import *
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from artiq.language.units import ms, us, ns
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from artiq.coredevice.ad9912_reg import *
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@ -35,7 +35,7 @@ class AD9912:
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chip_select: KernelInvariant[int32]
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pll_n: KernelInvariant[int32]
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ftw_per_hz: KernelInvariant[float]
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sw: KernelInvariant[TTLOut]
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sw: KernelInvariant[Option[TTLOut]]
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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pll_n=10):
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@ -45,8 +45,9 @@ class AD9912:
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assert 4 <= chip_select <= 7
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self.chip_select = chip_select
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if sw_device:
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self.sw = dmgr.get(sw_device)
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# NAC3TODO: support no sw
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self.sw = Some(dmgr.get(sw_device))
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else:
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self.sw = none
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self.pll_n = pll_n
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sysclk = self.cpld.refclk / [1, 1, 2, 4][self.cpld.clk_div] * pll_n
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assert sysclk <= 1e9
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@ -67,7 +67,7 @@ class NAC3Devices(EnvExperiment):
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self.core.break_realtime()
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self.urukul0_cpld.init()
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self.urukul0_ch0.init()
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self.urukul0_ch0.sw.on()
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self.urukul0_ch0.sw.unwrap().on()
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for i in range(10):
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self.urukul0_ch0.set((10. + float(i))*MHz)
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self.urukul0_ch0.set_att(6.)
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