From 72932fccec813b231e6f7bd644078d33ee76f5f9 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Fri, 7 Oct 2016 15:40:00 +0200 Subject: [PATCH] phaser: fix sysref for 250 MHz sample rate --- artiq/examples/phaser/startup_kernel.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/artiq/examples/phaser/startup_kernel.py b/artiq/examples/phaser/startup_kernel.py index eb310ddf5..24b5b3fb5 100644 --- a/artiq/examples/phaser/startup_kernel.py +++ b/artiq/examples/phaser/startup_kernel.py @@ -57,13 +57,15 @@ class StartupKernel(EnvExperiment): 2*AD9516_OUT9_LVDS_CMOS_OUTPUT_POLARITY | 0*AD9516_OUT9_SELECT_LVDS_CMOS) - # sysref f_data*S/(K*F), dclk/32 - self.ad9154.clock_write(AD9516_DIVIDER_3_0, 15*AD9516_DIVIDER_3_HIGH_CYCLES_1 | - 15*AD9516_DIVIDER_3_LOW_CYCLES_1) + # sysref f_data*S/(K*F), dclk/64 + self.ad9154.clock_write(AD9516_DIVIDER_3_0, (32//2-1)*AD9516_DIVIDER_3_HIGH_CYCLES_1 | + (32//2-1)*AD9516_DIVIDER_3_LOW_CYCLES_1) self.ad9154.clock_write(AD9516_DIVIDER_3_1, 0*AD9516_DIVIDER_3_PHASE_OFFSET_1 | 0*AD9516_DIVIDER_3_PHASE_OFFSET_2) + self.ad9154.clock_write(AD9516_DIVIDER_3_2, (2//2-1)*AD9516_DIVIDER_3_HIGH_CYCLES_2 | + (2//2-1)*AD9516_DIVIDER_3_LOW_CYCLES_2) self.ad9154.clock_write(AD9516_DIVIDER_3_3, 0*AD9516_DIVIDER_3_NOSYNC | - 0*AD9516_DIVIDER_3_BYPASS_1 | 1*AD9516_DIVIDER_3_BYPASS_2) + 0*AD9516_DIVIDER_3_BYPASS_1 | 0*AD9516_DIVIDER_3_BYPASS_2) self.ad9154.clock_write(AD9516_DIVIDER_3_4, 1*AD9516_DIVIDER_3_DCCOFF) self.ad9154.clock_write(AD9516_OUT6, 1*AD9516_OUT6_LVDS_OUTPUT_CURRENT | 2*AD9516_OUT6_LVDS_CMOS_OUTPUT_POLARITY |