From 7166ca82d16bb90ed519c636a8b47caa91bb87fc Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 30 Nov 2014 22:31:55 +0800 Subject: [PATCH] targets/ARTIQMiniSoC: map RTIO CSRs directly on Wishbone (reduces programming time by 30%) --- soc/targets/artiq.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/soc/targets/artiq.py b/soc/targets/artiq.py index f56f59539..46ce96584 100644 --- a/soc/targets/artiq.py +++ b/soc/targets/artiq.py @@ -1,4 +1,5 @@ from migen.fhdl.std import * +from migen.bank import wbgen from mibuild.generic_platform import * from misoclib import gpio @@ -70,7 +71,7 @@ TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG; class ARTIQMiniSoC(BaseSoC): csr_map = { - "rtio": 13 + "rtio": None # mapped on Wishbone instead } csr_map.update(BaseSoC.csr_map) @@ -101,6 +102,11 @@ class ARTIQMiniSoC(BaseSoC): clk_freq=125000000, ififo_depth=512) + rtio_csrs = self.rtio.get_csrs() + self.submodules.rtiowb = wbgen.Bank(rtio_csrs) + self.add_wb_slave(lambda a: a[26:29] == 2, self.rtiowb.bus) + self.add_cpu_csr_region("rtio", 0xa0000000, 32, rtio_csrs) + if with_test_gen: self.submodules.test_gen = _TestGen(platform.request("ttl", 8))