transforms.devirtualizer → analyses.devirtualization.

This commit is contained in:
whitequark 2015-10-09 00:29:31 +03:00
parent 962dd9de13
commit 7043b333a7
4 changed files with 5 additions and 6 deletions

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@ -1 +1,2 @@
from .domination import DominatorTree
from .devirtualization import Devirtualization

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@ -102,7 +102,7 @@ class MethodResolver(algorithm.Visitor):
continue
_advance(self.method_map, (instance_type, target.attr), value)
class Devirtualizer:
class Devirtualization:
def __init__(self):
self.variable_map = dict()
self.method_map = dict()
@ -114,4 +114,3 @@ class Devirtualizer:
method_resolver = MethodResolver(self.variable_map, self.method_map)
method_resolver.visit(node)
print(self.method_map)

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@ -10,7 +10,7 @@ string and infers types for it using a trivial :module:`prelude`.
import os
from pythonparser import source, diagnostic, parse_buffer
from . import prelude, types, transforms, validators
from . import prelude, types, transforms, analyses, validators
class Source:
def __init__(self, source_buffer, engine=None):
@ -57,7 +57,7 @@ class Module:
ref_period=ref_period)
dead_code_eliminator = transforms.DeadCodeEliminator(engine=self.engine)
local_access_validator = validators.LocalAccessValidator(engine=self.engine)
devirtualizer = transforms.Devirtualizer()
devirtualization = analyses.Devirtualization()
self.name = src.name
self.globals = src.globals
@ -66,7 +66,7 @@ class Module:
monomorphism_validator.visit(src.typedtree)
escape_validator.visit(src.typedtree)
iodelay_estimator.visit_fixpoint(src.typedtree)
devirtualizer.visit(src.typedtree)
devirtualization.visit(src.typedtree)
self.artiq_ir = artiq_ir_generator.visit(src.typedtree)
dead_code_eliminator.process(self.artiq_ir)
local_access_validator.process(self.artiq_ir)

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@ -3,6 +3,5 @@ from .inferencer import Inferencer
from .int_monomorphizer import IntMonomorphizer
from .iodelay_estimator import IODelayEstimator
from .artiq_ir_generator import ARTIQIRGenerator
from .devirtualizer import Devirtualizer
from .dead_code_eliminator import DeadCodeEliminator
from .llvm_ir_generator import LLVMIRGenerator