From 7028d852559006d6b308b692fd86d2e868a5a339 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=A9bastien=20Bourdeauducq?= Date: Fri, 27 Feb 2015 18:02:21 -0700 Subject: [PATCH] targets/ppro: disable L2 --- soc/targets/artiq_ppro.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/soc/targets/artiq_ppro.py b/soc/targets/artiq_ppro.py index 7d0f9c021..8c6749a46 100644 --- a/soc/targets/artiq_ppro.py +++ b/soc/targets/artiq_ppro.py @@ -92,7 +92,8 @@ class ARTIQMiniSoC(BaseSoC): } csr_map.update(BaseSoC.csr_map) - def __init__(self, platform, cpu_type="or1k", ramcon_type="minicon", + def __init__(self, platform, cpu_type="or1k", + ramcon_type="minicon", with_l2=False, with_test_gen=False, **kwargs): BaseSoC.__init__(self, platform, cpu_type=cpu_type, ramcon_type=ramcon_type,