devices: let corecom create runtime environment, add dummy corecom

This commit is contained in:
Sebastien Bourdeauducq 2014-07-15 11:20:13 -06:00
parent 529b83bb58
commit 6f28ab2cc6
5 changed files with 40 additions and 6 deletions

View File

@ -5,7 +5,9 @@ from artiq.compiler.interleave import interleave
from artiq.compiler.ir import get_runtime_binary
class Core:
def __init__(self, runtime_env, core_com):
def __init__(self, core_com, runtime_env=None):
if runtime_env is None:
runtime_env = core_com.get_runtime_env()
self.runtime_env = runtime_env
self.core_com = core_com

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@ -0,0 +1,28 @@
from operator import itemgetter
from artiq.devices.runtime import LinkInterface
from artiq.language.units import ns
class _RuntimeEnvironment(LinkInterface):
def __init__(self, ref_period):
self.ref_period = ref_period
def emit_object(self):
return str(self.module)
class CoreCom:
def get_runtime_env(self):
return _RuntimeEnvironment(10*ns)
def run(self, kcode):
print("================")
print(" LLVM IR")
print("================")
print(kcode)
def serve(self, rpc_map):
print("================")
print(" RPC map")
print("================")
for k, v in sorted(rpc_map.items(), key=itemgetter(0)):
print(str(k)+" -> "+str(v))

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@ -26,7 +26,7 @@ def _str_to_functype(s):
type_args.append(_chr_to_type[c]())
return var_arg_fixcount, lc.Type.function(type_ret, type_args, var_arg=var_arg_fixcount is not None)
class Environment:
class LinkInterface:
def set_module(self, module):
self.var_arg_fixcount = dict()
for func_name, func_type_str in _syscalls:
@ -45,6 +45,10 @@ class Environment:
+ args[fixcount:]
return builder.call(self.module.get_function_named("__syscall_"+syscall_name), args)
class Environment(LinkInterface):
def __init__(self, ref_period):
self.ref_period = ref_period
def emit_object(self):
tm = lt.TargetMachine.new(triple="or1k", cpu="generic")
return tm.emit_object(self.module)

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@ -28,9 +28,9 @@ class CompilerTest(MPO):
self.print_done()
if __name__ == "__main__":
from artiq.devices import core, dds_core
from artiq.devices import corecom_dummy, core, dds_core
coredev = core.Core()
coredev = core.Core(corecom_dummy.CoreCom())
exp = CompilerTest(
core=coredev,
a=dds_core.DDS(coredev, 0, 0),

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@ -1,5 +1,5 @@
from artiq.language.core import MPO, kernel
from artiq.devices import corecom_serial, runtime, core, gpio_core
from artiq.devices import corecom_serial, core, gpio_core
class CompilerTest(MPO):
parameters = "led"
@ -29,7 +29,7 @@ class CompilerTest(MPO):
if __name__ == "__main__":
with corecom_serial.CoreCom() as com:
coredev = core.Core(runtime.Environment(), com)
coredev = core.Core(com)
exp = CompilerTest(
core=coredev,
led=gpio_core.GPIOOut(coredev, 0)