M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-29 05:03:34 +08:00
Code Issues Projects Releases Wiki Activity

coredevice.ttl: add missed int64 conversion.

Browse Source
This commit is contained in:
whitequark 2016-03-04 08:37:38 +00:00
parent 7ff0c89d51
commit 6e44c5424d
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/coredevice/ttl.py
View File

@ -238,7 +238,7 @@ class TTLClockGen:
# in RTIO cycles
self.previous_timestamp = int(0, width=64)
self.acc_width = 24
self.acc_width = int(24, width=64)
@portable
def frequency_to_ftw(self, frequency):