M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

drtio: fix GTH CPLL reset

This commit is contained in:
Sebastien Bourdeauducq 2017-12-30 12:13:43 +08:00
parent 379d29561b
commit 6e0288e568
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/drtio/transceiver/gth_ultrascale.py
View File

@ -39,8 +39,10 @@ class GTHSingle(Module):
rx_init = ClockDomainsRenamer("rtio_tx")(GTHInit(rtio_clk_freq, True)) rx_init = ClockDomainsRenamer("rtio_tx")(GTHInit(rtio_clk_freq, True))
self.submodules += tx_init, rx_init self.submodules += tx_init, rx_init
cpll_reset = Signal()
cpll_lock = Signal() cpll_lock = Signal()
self.comb += [ self.comb += [
cpll_reset.eq(tx_init.pllreset),
tx_init.plllock.eq(cpll_lock), tx_init.plllock.eq(cpll_lock),
rx_init.plllock.eq(cpll_lock) rx_init.plllock.eq(cpll_lock)
] ]
@ -77,7 +79,7 @@ class GTHSingle(Module):
p_RXOUT_DIV=2, p_RXOUT_DIV=2,
p_TXOUT_DIV=2, p_TXOUT_DIV=2,
i_CPLLRESET=0, i_CPLLRESET=0,
i_CPLLPD=0, i_CPLLPD=cpll_reset,
o_CPLLLOCK=cpll_lock, o_CPLLLOCK=cpll_lock,
i_CPLLLOCKEN=1, i_CPLLLOCKEN=1,
i_CPLLREFCLKSEL=0b001, i_CPLLREFCLKSEL=0b001,