M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

sayma_amc: enable DRTIO switching

This commit is contained in:
Sebastien Bourdeauducq 2019-10-04 22:55:23 +08:00
parent 0cf8a46bbd
commit 6cb0f5de59
1 changed files with 49 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
artiq/gateware/targets/sayma_amc.py
View File

@ -358,27 +358,58 @@ class Satellite(BaseSoC, RTMCommon):
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) drtioaux_csr_group = []
self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer()) drtioaux_memory_group = []
self.submodules.drtiosat = rx0(DRTIOSatellite( drtiorep_csr_group = []
self.rtio_tsc, self.drtio_transceiver.channels[0], drtio_cri = []
self.rx_synchronizer)) for i in range(len(self.drtio_transceiver.channels)):
self.csr_devices.append("drtiosat") coreaux_name = "drtioaux" + str(i)
self.submodules.drtioaux0 = rx0(DRTIOAuxController( memory_name = "drtioaux" + str(i) + "_mem"
self.drtiosat.link_layer)) drtioaux_csr_group.append(coreaux_name)
self.csr_devices.append("drtioaux0") drtioaux_memory_group.append(memory_name)
self.add_wb_slave(self.mem_map["drtioaux"], 0x800,
self.drtioaux0.bus) cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800)
if i == 0:
self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
core = cdr(DRTIOSatellite(
self.rtio_tsc, self.drtio_transceiver.channels[i],
self.rx_synchronizer))
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
else:
corerep_name = "drtiorep" + str(i-1)
drtiorep_csr_group.append(corerep_name)
core = cdr(DRTIORepeater(
self.rtio_tsc, self.drtio_transceiver.channels[i]))
setattr(self.submodules, corerep_name, core)
drtio_cri.append(core.cri)
self.csr_devices.append(corerep_name)
coreaux = cdr(DRTIOAuxController(core.link_layer))
setattr(self.submodules, coreaux_name, coreaux)
self.csr_devices.append(coreaux_name)
memory_address = self.mem_map["drtioaux"] + 0x800*i
self.add_wb_slave(memory_address, 0x800,
coreaux.bus)
self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
self.config["HAS_DRTIO"] = None self.config["HAS_DRTIO"] = None
self.add_csr_group("drtioaux", ["drtioaux0"]) self.config["HAS_DRTIO_ROUTING"] = None
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"]) self.add_csr_group("drtioaux", drtioaux_csr_group)
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.add_csr_group("drtiorep", drtiorep_csr_group)
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels) self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
self.comb += [ self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
self.drtiosat.cri.connect(self.local_io.cri), self.submodules.cri_con = rtio.CRIInterconnectShared(
self.drtiosat.async_errors.eq(self.local_io.async_errors), [self.drtiosat.cri],
] [self.local_io.cri] + drtio_cri,
mode="sync", enable_routing=True)
self.csr_devices.append("cri_con")
self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
self.csr_devices.append("routing_table")
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
if self.hw_rev == "v2.0": if self.hw_rev == "v2.0":