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https://github.com/m-labs/artiq.git
synced 2024-12-25 03:08:27 +08:00
satman: fix targets without drtio routing
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parent
c9e3771cd5
commit
6c0ff9a912
@ -789,7 +789,8 @@ pub extern fn main() -> i32 {
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}
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kernelmgr.process_kern_requests(&mut router, &routing_table, rank, destination, &mut dma_manager);
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#[cfg(has_drtio_routing)]
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if let Some((repno, packet)) = router.get_downstream_packet() {
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if let Err(e) = repeaters[repno].aux_send(&packet) {
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warn!("[REP#{}] Error when sending packet to satellite ({:?})", repno, e)
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@ -1,5 +1,6 @@
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use alloc::{vec::Vec, collections::vec_deque::VecDeque};
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use board_artiq::{drtioaux, drtio_routing};
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#[cfg(has_drtio_routing)]
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use board_misoc::csr;
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use core::cmp::min;
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use proto_artiq::drtioaux_proto::PayloadStatus;
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@ -72,6 +73,7 @@ impl Sliceable {
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pub struct Router {
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upstream_queue: VecDeque<drtioaux::Packet>,
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local_queue: VecDeque<drtioaux::Packet>,
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#[cfg(has_drtio_routing)]
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downstream_queue: VecDeque<(usize, drtioaux::Packet)>,
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upstream_notified: bool,
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}
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@ -81,6 +83,7 @@ impl Router {
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Router {
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upstream_queue: VecDeque::new(),
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local_queue: VecDeque::new(),
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#[cfg(has_drtio_routing)]
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downstream_queue: VecDeque::new(),
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upstream_notified: false,
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}
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@ -90,14 +93,14 @@ impl Router {
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// messages are always buffered for both upstream and downstream
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pub fn route(&mut self, packet: drtioaux::Packet,
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_routing_table: &drtio_routing::RoutingTable, _rank: u8,
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_self_destination: u8
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self_destination: u8
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) {
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let destination = packet.routable_destination();
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#[cfg(has_drtio_routing)]
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{
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let destination = packet.routable_destination();
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if let Some(destination) = destination {
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let hop = _routing_table.0[destination as usize][_rank as usize] as usize;
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if destination == _self_destination {
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if destination == self_destination {
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self.local_queue.push_back(packet);
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} else if hop > 0 && hop < csr::DRTIOREP.len() {
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let repno = (hop - 1) as usize;
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@ -111,7 +114,11 @@ impl Router {
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}
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#[cfg(not(has_drtio_routing))]
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{
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self.upstream_queue.push_back(packet);
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if destination == Some(self_destination) {
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self.local_queue.push_back(packet);
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} else {
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self.upstream_queue.push_back(packet);
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}
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}
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}
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@ -166,6 +173,7 @@ impl Router {
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packet
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}
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#[cfg(has_drtio_routing)]
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pub fn get_downstream_packet(&mut self) -> Option<(usize, drtioaux::Packet)> {
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self.downstream_queue.pop_front()
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}
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