M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 11:18:27 +08:00
Code Issues Projects Releases Wiki Activity

rtio: use same reset for counter_rtio whatever the interface delay is

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2016-12-15 09:28:13 +08:00
parent 15b48be6e4
commit 6b998581cc
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
artiq/gateware/rtio/core.py
View File

@ -162,8 +162,8 @@ class _OutputManager(Module):
# latency compensation # latency compensation
if interface.delay: if interface.delay:
counter_rtio = Signal.like(counter.value_rtio) counter_rtio = Signal.like(counter.value_rtio)
self.sync.rio += counter_rtio.eq(counter.value_rtio - self.sync.rtio += counter_rtio.eq(counter.value_rtio -
interface.delay + 1) interface.delay + 1)
else: else:
counter_rtio = counter.value_rtio counter_rtio = counter.value_rtio
@ -221,8 +221,8 @@ class _InputManager(Module):
# latency compensation # latency compensation
if interface.delay: if interface.delay:
counter_rtio = Signal.like(counter.value_rtio) counter_rtio = Signal.like(counter.value_rtio)
self.sync.rio += counter_rtio.eq(counter.value_rtio - self.sync.rtio += counter_rtio.eq(counter.value_rtio -
interface.delay + 1) interface.delay + 1)
else: else:
counter_rtio = counter.value_rtio counter_rtio = counter.value_rtio