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https://github.com/m-labs/artiq.git
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firmware: ad9154 timeouts and logging
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parent
417708af90
commit
6b7e6a53f7
3
artiq/firmware/Cargo.lock
generated
3
artiq/firmware/Cargo.lock
generated
@ -13,6 +13,9 @@ version = "0.0.0"
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[[package]]
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name = "board"
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version = "0.0.0"
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dependencies = [
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"log 0.3.6 (registry+https://github.com/rust-lang/crates.io-index)",
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]
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[[package]]
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name = "byteorder"
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@ -6,3 +6,6 @@ version = "0.0.0"
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[lib]
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name = "board"
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path = "lib.rs"
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[dependencies]
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log = { version = "0.3", default-features = false }
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@ -325,7 +325,12 @@ fn dac_setup() -> Result<(), &'static str> {
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// 1*ad9154_reg::ENABLE_SERDESPLL | 1*ad9154_reg::RECAL_SERDESPLL)
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write(ad9154_reg::SERDESPLL_ENABLE_CNTRL,
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1*ad9154_reg::ENABLE_SERDESPLL | 0*ad9154_reg::RECAL_SERDESPLL);
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while read(ad9154_reg::PLL_STATUS) & ad9154_reg::SERDES_PLL_LOCK_RB == 0 {}
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let t = clock::get_ms();
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while read(ad9154_reg::PLL_STATUS) & ad9154_reg::SERDES_PLL_LOCK_RB == 0 {
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if clock::get_ms() > t + 200 {
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return Err("SERDES PLL lock timeout");
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}
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}
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write(ad9154_reg::EQ_BIAS_REG, 0x22*ad9154_reg::EQ_BIAS_RESERVED |
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1*ad9154_reg::EQ_POWER_MODE);
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@ -421,7 +426,12 @@ fn cfg() -> Result<(), &'static str> {
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clock::spin_us(10000);
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jesd_enable(true);
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monitor();
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while !jesd_ready() {}
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let t = clock::get_ms();
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while !jesd_ready() {
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if clock::get_ms() > t + 200 {
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return Err("JESD ready timeout");
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}
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}
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clock::spin_us(10000);
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if read(ad9154_reg::CODEGRPSYNCFLG) != 0x0f {
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return Err("bad CODEGRPSYNCFLG")
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@ -444,10 +454,11 @@ fn cfg() -> Result<(), &'static str> {
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pub fn init() -> Result<(), &'static str> {
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spi_setup();
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for _ in 0..99 {
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for i in 0..99 {
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let outcome = cfg();
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if outcome.is_ok() {
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return outcome
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match outcome {
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Ok(_) => return outcome,
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Err(e) => warn!("config attempt #{} failed ({}), retrying", i, e)
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}
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}
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cfg()
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@ -1,6 +1,9 @@
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#![feature(asm)]
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#![no_std]
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#[macro_use]
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extern crate log;
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use core::{cmp, ptr, str};
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
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