From 6b63322106e25b098c4c0cc4c4edc87cd1942f05 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 17 Mar 2017 07:23:45 +0000 Subject: [PATCH] gateware: reverse SDRAM words in RTIO DMA engine. --- artiq/gateware/rtio/dma.py | 6 +++++- artiq/gateware/test/rtio/test_dma.py | 10 ++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/rtio/dma.py b/artiq/gateware/rtio/dma.py index fc12b5b05..8e562c903 100644 --- a/artiq/gateware/rtio/dma.py +++ b/artiq/gateware/rtio/dma.py @@ -7,6 +7,10 @@ from misoc.interconnect import stream, wishbone from artiq.gateware.rtio import cri +def _reverse_signal(s): + return Cat(s[i] for i in reversed(range(len(s)))) + + class WishboneReader(Module): def __init__(self, bus=None): if bus is None: @@ -35,7 +39,7 @@ class WishboneReader(Module): If(self.source.ack, data_reg_loaded.eq(0)), If(bus.ack, data_reg_loaded.eq(1), - self.source.data.eq(bus.dat_r), + self.source.data.eq(_reverse_signal(bus.dat_r)), self.source.eop.eq(self.sink.eop) ) ] diff --git a/artiq/gateware/test/rtio/test_dma.py b/artiq/gateware/test/rtio/test_dma.py index db2cd903b..c52026c5b 100644 --- a/artiq/gateware/test/rtio/test_dma.py +++ b/artiq/gateware/test/rtio/test_dma.py @@ -23,7 +23,7 @@ def encode_record(channel, timestamp, address, data): r += encode_n(channel, 3, 3) r += encode_n(timestamp, 8, 8) r += encode_n(address, 2, 2) - r += encode_n(data, 1, 64) + r += encode_n(data, 4, 64) return encode_n(len(r)+1, 1, 1) + r @@ -33,7 +33,12 @@ def pack(x, size): n = 0 for j, w in enumerate(x[i*size:(i+1)*size]): n |= w << j*8 - r.append(n) + nr = 0 + for i in range(size*8): + if (n >> i) & 1: nr |= 1 << (size*8 - 1 - i) + # print("{:064x}".format(n)) + # print("{:064x}".format(nr)) + r.append(nr) return r @@ -48,6 +53,7 @@ class TB(Module): def __init__(self, ws): sequence = [b for write in test_writes for b in encode_record(*write)] sequence.append(0) + # print(sequence) sequence = pack(sequence, ws) bus = wishbone.Interface(ws*8)