M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 2
Code Issues Projects Releases Wiki Activity

firmware/ad9154: use fixed hmc7043 sysref phase (found with scan)

This commit is contained in:
Florent Kermarrec 2018-05-12 00:12:59 +02:00
parent 3c49eba0a0
commit 6b4bbe31f7
1 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/firmware/libboard_artiq/ad9154.rs
View File

@ -608,7 +608,8 @@ fn dac_cfg_retry(dacno: u8) -> Result<(), &'static str> {
dac_cfg(dacno) dac_cfg(dacno)
} }
fn dac_sysref_cfg(dacno: u8) { #[allow(dead_code)]
fn dac_sysref_scan(dacno: u8) {
let mut sync_error_last = 0u16; let mut sync_error_last = 0u16;
let mut phase_min_found = false; let mut phase_min_found = false;
let mut phase_min = 0u16; let mut phase_min = 0u16;
@ -646,6 +647,11 @@ fn dac_sysref_cfg(dacno: u8) {
hmc7043::cfg_dac_sysref(dacno, phase_opt); hmc7043::cfg_dac_sysref(dacno, phase_opt);
} }
fn dac_sysref_cfg(dacno: u8, phase: u16) {
info!("AD9154-{} setting SYSREF phase to {}", dacno, phase);
hmc7043::cfg_dac_sysref(dacno, phase);
}
pub fn init() -> Result<(), &'static str> { pub fn init() -> Result<(), &'static str> {
// Release the JESD clock domain reset late, as we need to // Release the JESD clock domain reset late, as we need to
// set up clock chips before. // set up clock chips before.
@ -654,9 +660,9 @@ pub fn init() -> Result<(), &'static str> {
for dacno in 0..csr::AD9154.len() { for dacno in 0..csr::AD9154.len() {
let dacno = dacno as u8; let dacno = dacno as u8;
debug!("setting up AD9154-{} DAC...", dacno); debug!("setting up AD9154-{} DAC...", dacno);
dac_sysref_cfg(dacno, 88);
dac_cfg_retry(dacno)?; dac_cfg_retry(dacno)?;
dac_prbs(dacno)?; dac_prbs(dacno)?;
dac_sysref_cfg(dacno);
dac_cfg_retry(dacno)?; dac_cfg_retry(dacno)?;
} }