From 6aaa8bf9d95d0a337a000c14b0465ee41913bb9e Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 4 Mar 2018 23:20:13 +0800 Subject: [PATCH] drtio: fix link error generation --- artiq/gateware/drtio/rt_controller_master.py | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/artiq/gateware/drtio/rt_controller_master.py b/artiq/gateware/drtio/rt_controller_master.py index 0cfaaeafc..ea325a1b8 100644 --- a/artiq/gateware/drtio/rt_controller_master.py +++ b/artiq/gateware/drtio/rt_controller_master.py @@ -63,11 +63,6 @@ class RTController(Module): self.comb += self.cd_rtio_with_rst.clk.eq(ClockSignal("rtio")) self.specials += AsyncResetSynchronizer(self.cd_rtio_with_rst, local_reset) - self.comb += [ - self.cri.o_status[2].eq(~self.csrs.link_up.storage), - self.cri.i_status[3].eq(~self.csrs.link_up.storage) - ] - # protocol errors err_unknown_packet_type = Signal() err_packet_truncated = Signal() @@ -126,7 +121,7 @@ class RTController(Module): o_status_underflow = Signal() self.comb += [ self.cri.o_status.eq(Cat( - o_status_wait, o_status_underflow)), + o_status_wait, o_status_underflow, ~self.csrs.link_up.storage)), self.csrs.o_wait.status.eq(o_status_wait) ] o_underflow_set = Signal() @@ -151,7 +146,8 @@ class RTController(Module): i_status_overflow = Signal() i_status_wait_status = Signal() self.comb += self.cri.i_status.eq(Cat( - i_status_wait_event, i_status_overflow, i_status_wait_status)) + i_status_wait_event, i_status_overflow, i_status_wait_status, + ~self.csrs.link_up.storage)) load_read_reply = Signal() self.sync.sys_with_rst += [