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Remove last vestiges of nist_qc1.

This commit is contained in:
whitequark 2016-11-21 15:36:22 +00:00
parent 5e8888d5f3
commit 6aa5d9f6c6
7 changed files with 49 additions and 114 deletions
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7
artiq/gateware/ad9xxx.py
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@ -24,13 +24,6 @@ class AD9xxx(Module):
Design: Design:
All IO pads are registered. All IO pads are registered.
With QC1 adapter:
LVDS driver/receiver propagation delays are 3.6+4.5 ns max
LVDS state transition delays are 20, 15 ns max
Schmitt trigger delays are 6.4ns max
Round-trip addr A setup (> RX, RD, D to Z), RD prop, D valid (< D
valid), D prop is ~15 + 10 + 20 + 10 = 55ns
""" """
def __init__(self, pads, def __init__(self, pads,
read_wait_cycles=10, hiz_wait_cycles=3, read_wait_cycles=10, hiz_wait_cycles=3,

54
artiq/gateware/nist_qc1.py
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@ -1,54 +0,0 @@
from migen.build.generic_platform import *
papilio_adapter_io = [
("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),
# to feed the 125 MHz clock (preferrably from DDS SYNC_CLK)
# to the FPGA, use the xtrig pair.
#
# on papiliopro-adapter, xtrig (C:12) is connected to a GCLK
#
# on pipistrello, C:15 is the only GCLK in proximity, used as a button
# input, BTN2/PMT2 in papiliopro-adapter
# either improve the DDS box to feed 125MHz into the PMT2 pair, or:
#
# * disconnect C:15 from its periphery on the adapter board
# * bridge C:15 to the xtrig output of the transciever
# * optionally, disconnect C:12 from its periphery
("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
("pmt", 2, Pins("C:15"), IOStandard("LVTTL")), # rarely equipped
("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
("ttl", 2, Pins("C:9"), IOStandard("LVTTL")),
("ttl", 3, Pins("C:8"), IOStandard("LVTTL")),
("ttl", 4, Pins("C:7"), IOStandard("LVTTL")),
("ttl", 5, Pins("C:6"), IOStandard("LVTTL")),
("ttl", 6, Pins("C:5"), IOStandard("LVTTL")),
("ttl", 7, Pins("C:4"), IOStandard("LVTTL")),
("ttl_l_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
("ttl", 8, Pins("C:3"), IOStandard("LVTTL")),
("ttl", 9, Pins("C:2"), IOStandard("LVTTL")),
("ttl", 10, Pins("C:1"), IOStandard("LVTTL")),
("ttl", 11, Pins("C:0"), IOStandard("LVTTL")),
("ttl", 12, Pins("B:4"), IOStandard("LVTTL")),
("ttl", 13, Pins("A:11"), IOStandard("LVTTL")),
("ttl", 14, Pins("B:5"), IOStandard("LVTTL")),
("ttl", 15, Pins("A:10"), IOStandard("LVTTL")),
("ttl_h_tx_en", 0, Pins("B:6"), IOStandard("LVTTL")),
("dds", 0,
Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
Subsignal("p", Pins("A:8 B:12")),
Subsignal("fud_n", Pins("B:11")),
Subsignal("wr_n", Pins("A:4")),
Subsignal("rd_n", Pins("B:13")),
Subsignal("rst_n", Pins("A:3")),
IOStandard("LVTTL")),
]

56
artiq/gateware/targets/pipistrello.py
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@ -18,7 +18,7 @@ from misoc.targets.pipistrello import (BaseSoC, soc_pipistrello_args,
from misoc.integration.builder import builder_args, builder_argdict from misoc.integration.builder import builder_args, builder_argdict
from artiq.gateware.soc import AMPSoC, build_artiq_soc from artiq.gateware.soc import AMPSoC, build_artiq_soc
from artiq.gateware import rtio, nist_qc1 from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds, spi from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds, spi
from artiq import __version__ as artiq_version from artiq import __version__ as artiq_version
@ -61,14 +61,14 @@ class _RTIOCRG(Module, AutoCSR):
f = Fraction(rtio_f, clk_freq) f = Fraction(rtio_f, clk_freq)
rtio_internal_clk = Signal() rtio_internal_clk = Signal()
rtio_external_clk = Signal() rtio_external_clk = Signal()
pmt2 = platform.request("pmt", 2) ext_clk = platform.request("ext_clk")
dcm_locked = Signal() dcm_locked = Signal()
rtio_clk = Signal() rtio_clk = Signal()
pll_locked = Signal() pll_locked = Signal()
pll = Signal(3) pll = Signal(3)
pll_fb = Signal() pll_fb = Signal()
self.specials += [ self.specials += [
Instance("IBUFG", i_I=pmt2, o_O=rtio_external_clk), Instance("IBUFG", i_I=ext_clk, o_O=rtio_external_clk),
Instance("DCM_CLKGEN", p_CLKFXDV_DIVIDE=2, Instance("DCM_CLKGEN", p_CLKFXDV_DIVIDE=2,
p_CLKFX_DIVIDE=f.denominator, p_CLKFX_MD_MAX=float(f), p_CLKFX_DIVIDE=f.denominator, p_CLKFX_MD_MAX=float(f),
p_CLKFX_MULTIPLY=f.numerator, p_CLKIN_PERIOD=1e9/clk_freq, p_CLKFX_MULTIPLY=f.numerator, p_CLKIN_PERIOD=1e9/clk_freq,
@ -124,7 +124,30 @@ TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
rtio_clk=self.cd_rtio.clk) rtio_clk=self.cd_rtio.clk)
class NIST_QC1(BaseSoC, AMPSoC): _ttl_io = [
("ext_clk", 0, Pins("C:15"), IOStandard("LVTTL")),
("ttl", 0, Pins("B:0"), IOStandard("LVTTL")),
("ttl", 1, Pins("B:1"), IOStandard("LVTTL")),
("ttl", 2, Pins("B:2"), IOStandard("LVTTL")),
("ttl", 3, Pins("B:3"), IOStandard("LVTTL")),
("ttl", 4, Pins("B:4"), IOStandard("LVTTL")),
("ttl", 5, Pins("B:5"), IOStandard("LVTTL")),
("ttl", 6, Pins("B:6"), IOStandard("LVTTL")),
("ttl", 7, Pins("B:7"), IOStandard("LVTTL")),
("ttl", 8, Pins("B:8"), IOStandard("LVTTL")),
("ttl", 9, Pins("B:9"), IOStandard("LVTTL")),
("ttl", 10, Pins("B:10"), IOStandard("LVTTL")),
("ttl", 11, Pins("B:11"), IOStandard("LVTTL")),
("ttl", 12, Pins("B:12"), IOStandard("LVTTL")),
("ttl", 13, Pins("B:13"), IOStandard("LVTTL")),
("ttl", 14, Pins("B:14"), IOStandard("LVTTL")),
("ttl", 15, Pins("B:15"), IOStandard("LVTTL")),
]
class Demo(BaseSoC, AMPSoC):
mem_map = { mem_map = {
"timer_kernel": 0x10000000, # (shadow @0x90000000) "timer_kernel": 0x10000000, # (shadow @0x90000000)
"rtio": 0x20000000, # (shadow @0xa0000000) "rtio": 0x20000000, # (shadow @0xa0000000)
@ -148,29 +171,16 @@ class NIST_QC1(BaseSoC, AMPSoC):
platform.toolchain.ise_commands += """ platform.toolchain.ise_commands += """
trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
""" """
platform.add_extension(nist_qc1.papilio_adapter_io) platform.add_extension(_ttl_io)
platform.add_extension(_pmod_spi) platform.add_extension(_pmod_spi)
self.submodules.leds = gpio.GPIOOut(platform.request("user_led", 4)) self.submodules.leds = gpio.GPIOOut(platform.request("user_led", 4))
self.comb += [
platform.request("ttl_l_tx_en").eq(1),
platform.request("ttl_h_tx_en").eq(1)
]
self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq) self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
self.csr_devices.append("rtio_crg") self.csr_devices.append("rtio_crg")
# RTIO channels # RTIO channels
rtio_channels = [] rtio_channels = []
# pmt1 can run on a 8x serdes if pmt0 is not used
for i in range(2):
phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
self.rtio_crg.rtiox4_stb)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
ofifo_depth=4))
# the last TTL is used for ClockGen # the last TTL is used for ClockGen
for i in range(15): for i in range(15):
if i in (0, 1): if i in (0, 1):
@ -185,10 +195,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
self.submodules += phy self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128)) rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=128))
phy = ttl_simple.Output(platform.request("ext_led", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=4))
for led_number in range(4): for led_number in range(4):
phy = ttl_simple.Output(platform.request("user_led", led_number)) phy = ttl_simple.Output(platform.request("user_led", led_number))
self.submodules += phy self.submodules += phy
@ -212,7 +218,6 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
# RTIO logic # RTIO logic
self.submodules.rtio = rtio.RTIO(rtio_channels) self.submodules.rtio = rtio.RTIO(rtio_channels)
self.register_kernel_cpu_csrdevice("rtio") self.register_kernel_cpu_csrdevice("rtio")
self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer( self.submodules.rtio_analyzer = rtio.Analyzer(
@ -222,13 +227,12 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
def main(): def main():
parser = argparse.ArgumentParser( parser = argparse.ArgumentParser(
description="ARTIQ core device builder / Pipistrello " description="ARTIQ core device builder / Pipistrello demo")
"+ NIST Ions QC1 hardware adapter")
builder_args(parser) builder_args(parser)
soc_pipistrello_args(parser) soc_pipistrello_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = NIST_QC1(**soc_pipistrello_argdict(args)) soc = Demo(**soc_pipistrello_argdict(args))
build_artiq_soc(soc, builder_argdict(args)) build_artiq_soc(soc, builder_argdict(args))

8
conda/artiq-pipistrello-nist_qc1/build.sh → conda/artiq-pipistrello-demo/build.sh
View File

@ -3,12 +3,12 @@
BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
[ -f $BUILD_SETTINGS_FILE ] && . $BUILD_SETTINGS_FILE [ -f $BUILD_SETTINGS_FILE ] && . $BUILD_SETTINGS_FILE
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/pipistrello-nist_qc1 SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/pipistrello-demo
mkdir -p $SOC_PREFIX mkdir -p $SOC_PREFIX
$PYTHON -m artiq.gateware.targets.pipistrello $MISOC_EXTRA_ISE_CMDLINE $PYTHON -m artiq.gateware.targets.pipistrello $MISOC_EXTRA_ISE_CMDLINE
cp misoc_nist_qc1_pipistrello/gateware/top.bit $SOC_PREFIX cp misoc_demo_pipistrello/gateware/top.bit $SOC_PREFIX
cp misoc_nist_qc1_pipistrello/software/bios/bios.bin $SOC_PREFIX cp misoc_demo_pipistrello/software/bios/bios.bin $SOC_PREFIX
cp misoc_nist_qc1_pipistrello/software/runtime/runtime.fbi $SOC_PREFIX cp misoc_demo_pipistrello/software/runtime/runtime.fbi $SOC_PREFIX
wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc6slx45.bit wget -P $SOC_PREFIX https://raw.githubusercontent.com/jordens/bscan_spi_bitstreams/master/bscan_spi_xc6slx45.bit

4
conda/artiq-pipistrello-nist_qc1/meta.yaml → conda/artiq-pipistrello-demo/meta.yaml
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@ -1,5 +1,5 @@
package: package:
name: artiq-pipistrello-nist_qc1 name: artiq-pipistrello-demo
version: {{ environ.get("GIT_DESCRIBE_TAG", "") }} version: {{ environ.get("GIT_DESCRIBE_TAG", "") }}
source: source:
@ -24,4 +24,4 @@ requirements:
about: about:
home: http://m-labs.hk/artiq home: http://m-labs.hk/artiq
license: GPL license: GPL
summary: 'Bitstream, BIOS and runtime for NIST_QC1 on the Pipistrello board' summary: 'Bitstream, BIOS and runtime for the Pipistrello board'

26
doc/manual/core_device.rst
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@ -141,33 +141,25 @@ The low-cost Pipistrello FPGA board can be used as a lower-cost but slower alter
.. warning:: The Pipistrello draws a high current over USB, and that current increases when the FPGA design is active. If you experience problems such as intermittent board freezes or USB errors, try connecting it to a self-powered USB hub. .. warning:: The Pipistrello draws a high current over USB, and that current increases when the FPGA design is active. If you experience problems such as intermittent board freezes or USB errors, try connecting it to a self-powered USB hub.
When plugged to an adapter, the NIST QC1 hardware can be used. The TTL lines are mapped to RTIO channels as follows: The TTL lines are mapped to RTIO channels as follows:
+--------------+------------+--------------+ +--------------+------------+--------------+
| RTIO channel | TTL line | Capability | | RTIO channel | TTL line | Capability |
+==============+============+==============+ +==============+============+==============+
| 0 | PMT0 | Input | | 0-14 | B0-14 | Output |
+--------------+------------+--------------+ +--------------+------------+--------------+
| 1 | PMT1 | Input | | 15 | USER_LED_1 | Output |
+--------------+------------+--------------+ +--------------+------------+--------------+
| 2-16 | TTL0-14 | Output | | 16 | USER_LED_2 | Output |
+--------------+------------+--------------+ +--------------+------------+--------------+
| 17 | EXT_LED | Output | | 17 | USER_LED_3 | Output |
+--------------+------------+--------------+ +--------------+------------+--------------+
| 18 | USER_LED_1 | Output | | 18 | USER_LED_4 | Output |
+--------------+------------+--------------+ +--------------+------------+--------------+
| 19 | USER_LED_2 | Output | | 19 | B15 | Clock |
+--------------+------------+--------------+
| 20 | USER_LED_3 | Output |
+--------------+------------+--------------+
| 21 | USER_LED_4 | Output |
+--------------+------------+--------------+
| 22 | TTL15 | Clock |
+--------------+------------+--------------+ +--------------+------------+--------------+
The input only limitation on channels 0 and 1 comes from the QC-DAQ adapter. When the adapter is not used (and physically unplugged from the Pipistrello board), the corresponding pins on the Pipistrello can be used as outputs. Do not configure these channels as outputs when the adapter is plugged, as this would cause electrical contention. The board can accept an external RTIO clock connected to C15.
The board can accept an external RTIO clock connected to PMT2. If the DDS box does not drive the PMT2 pair, use XTRIG and patch the XTRIG transceiver output on the adapter board onto C:15 disconnecting PMT2.
The board has one RTIO SPI bus on the PMOD connector, compliant to PMOD The board has one RTIO SPI bus on the PMOD connector, compliant to PMOD
Interface Type 2 (SPI) and 2A (expanded SPI): Interface Type 2 (SPI) and 2A (expanded SPI):
@ -175,5 +167,5 @@ Interface Type 2 (SPI) and 2A (expanded SPI):
+--------------+--------+--------+--------+--------+ +--------------+--------+--------+--------+--------+
| RTIO channel | CS_N | MOSI | MISO | CLK | | RTIO channel | CS_N | MOSI | MISO | CLK |
+==============+========+========+========+========+ +==============+========+========+========+========+
| 23 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 | | 16 | PMOD_0 | PMOD_1 | PMOD_2 | PMOD_3 |
+--------------+--------+--------+--------+--------+ +--------------+--------+--------+--------+--------+

8
doc/manual/installing.rst
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@ -43,13 +43,13 @@ Then prepare to create a new conda environment with the ARTIQ package and the ma
choose a suitable name for the environment, for example ``artiq-main`` if you intend to track the main label or ``artiq-2016-04-01`` if you consider the environment a snapshot of ARTIQ on 2016-04-01. choose a suitable name for the environment, for example ``artiq-main`` if you intend to track the main label or ``artiq-2016-04-01`` if you consider the environment a snapshot of ARTIQ on 2016-04-01.
Choose the package containing the binaries for your hardware: Choose the package containing the binaries for your hardware:
* ``artiq-pipistrello-nist_qc1`` for the `Pipistrello <http://pipistrello.saanlima.com/>`_ board with the NIST adapter to SCSI cables; AD9858 DDS chips are not supported anymore. * ``artiq-pipistrello-demo`` for the `Pipistrello <http://pipistrello.saanlima.com/>`_ board.
* ``artiq-kc705-nist_clock`` for the KC705 board with the NIST "clock" FMC backplane and AD9914 DDS chips. * ``artiq-kc705-nist_clock`` for the KC705 board with the NIST "clock" FMC backplane and AD9914 DDS chips.
* ``artiq-kc705-nist_qc2`` for the KC705 board with the NIST QC2 FMC backplane and AD9914 DDS chips. * ``artiq-kc705-nist_qc2`` for the KC705 board with the NIST QC2 FMC backplane and AD9914 DDS chips.
Conda will create the environment, automatically resolve, download, and install the necessary dependencies and install the packages you select:: Conda will create the environment, automatically resolve, download, and install the necessary dependencies and install the packages you select::
$ conda create -n artiq-main artiq-pipistrello-nist_qc1 $ conda create -n artiq-main artiq-pipistrello-demo
After the installation, activate the newly created environment by name. After the installation, activate the newly created environment by name.
On Unix:: On Unix::
@ -79,7 +79,7 @@ When upgrading ARTIQ or when testing different versions it is recommended that n
Keep previous environments around until you are certain that they are not needed anymore and a new environment is known to work correctly. Keep previous environments around until you are certain that they are not needed anymore and a new environment is known to work correctly.
You can create a new conda environment specifically to test a certain version of ARTIQ:: You can create a new conda environment specifically to test a certain version of ARTIQ::
$ conda create -n artiq-test-1.0rc2 artiq-pipistrello-nist_qc1=1.0rc2 $ conda create -n artiq-test-1.0rc2 artiq-pipistrello-demo=1.0rc2
Switching between conda environments using ``$ source deactivate artiq-1.0rc2`` and ``$ source activate artiq-1.0rc1`` is the recommended way to roll back to previous versions of ARTIQ. Switching between conda environments using ``$ source deactivate artiq-1.0rc2`` and ``$ source activate artiq-1.0rc1`` is the recommended way to roll back to previous versions of ARTIQ.
You can list the environments you have created using:: You can list the environments you have created using::
@ -131,7 +131,7 @@ Then, you can flash the board:
* For the Pipistrello board:: * For the Pipistrello board::
$ artiq_flash -t pipistrello -m nist_qc1 $ artiq_flash -t pipistrello -m demo
* For the KC705 board (selecting the appropriate hardware peripheral):: * For the KC705 board (selecting the appropriate hardware peripheral)::