mirror of https://github.com/m-labs/artiq.git
parent
f8627952c8
commit
68d16fc292
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@ -18,10 +18,18 @@ class _SerdesClocking(Module):
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# can use this clock to sample data
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# can use this clock to sample data
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if mode == "master":
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if mode == "master":
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self.specials += DDROutput(0, 1, self.refclk)
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self.specials += DDROutput(0, 1, self.refclk)
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self.specials += DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n)
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if hasattr(pads, "clk_p"):
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self.specials += DifferentialOutput(self.refclk, pads.clk_p, pads.clk_n)
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else:
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self.comb += pads.clk.eq(self.refclk)
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# In Slave mode, use the clock provided by Master
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# In Slave mode, use the clock provided by Master
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elif mode == "slave":
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elif mode == "slave":
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self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk)
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if hasattr(pads, "clk_p"):
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self.specials += DifferentialInput(pads.clk_p, pads.clk_n, self.refclk)
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else:
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self.comb += self.refclk.eq(pads.clk)
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else:
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raise ValueError
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class _SerdesTX(Module):
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class _SerdesTX(Module):
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@ -47,7 +55,10 @@ class _SerdesTX(Module):
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# Output data (on rising edge of sys_clk)
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# Output data (on rising edge of sys_clk)
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data = Signal()
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data = Signal()
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self.sync += data.eq(datapath.source.data)
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self.sync += data.eq(datapath.source.data)
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self.specials += DifferentialOutput(data, pads.tx_p, pads.tx_n)
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if hasattr(pads, "tx_p"):
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self.specials += DifferentialOutput(data, pads.tx_p, pads.tx_n)
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else:
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self.comb += pads.tx.eq(data)
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class _SerdesRX(Module):
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class _SerdesRX(Module):
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@ -67,7 +78,10 @@ class _SerdesRX(Module):
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# Input data (on rising edge of sys_clk)
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# Input data (on rising edge of sys_clk)
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data = Signal()
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data = Signal()
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data_d = Signal()
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data_d = Signal()
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self.specials += DifferentialInput(pads.rx_p, pads.rx_n, data)
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if hasattr(pads, "rx_p"):
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self.specials += DifferentialInput(pads.rx_p, pads.rx_n, data)
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else:
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self.comb += data.eq(pads.rx)
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self.sync += data_d.eq(data)
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self.sync += data_d.eq(data)
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# Datapath
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# Datapath
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@ -183,7 +183,7 @@ class SaymaRTM(Module):
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# AMC/RTM serwb
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# AMC/RTM serwb
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serwb_pads = platform.request("amc_rtm_serwb")
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serwb_pads = platform.request("amc_rtm_serwb")
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platform.add_period_constraint(serwb_pads.clk_p, 8.)
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platform.add_period_constraint(serwb_pads.clk, 8.)
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serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave")
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serwb_phy_rtm = serwb.genphy.SERWBPHY(platform.device, serwb_pads, mode="slave")
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self.submodules.serwb_phy_rtm = serwb_phy_rtm
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self.submodules.serwb_phy_rtm = serwb_phy_rtm
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self.comb += [
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self.comb += [
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