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gateware: extend mailbox to 3 entries.

This commit is contained in:
whitequark 2016-10-21 12:09:14 +00:00
parent 6aa13fbf25
commit 6872017449
2 changed files with 5 additions and 5 deletions
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8
artiq/gateware/amp/mailbox.py
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@ -3,19 +3,19 @@ from misoc.interconnect import wishbone
class Mailbox(Module): class Mailbox(Module):
def __init__(self): def __init__(self, size=1):
self.i1 = wishbone.Interface() self.i1 = wishbone.Interface()
self.i2 = wishbone.Interface() self.i2 = wishbone.Interface()
# # # # # #
value = Signal(32) values = Array([Signal(32) for _ in range(size)])
for i in self.i1, self.i2: for i in self.i1, self.i2:
self.sync += [ self.sync += [
i.dat_r.eq(value), i.dat_r.eq(values[i.adr]),
i.ack.eq(0), i.ack.eq(0),
If(i.cyc & i.stb & ~i.ack, If(i.cyc & i.stb & ~i.ack,
i.ack.eq(1), i.ack.eq(1),
If(i.we, value.eq(i.dat_w)) If(i.we, values[i.adr].eq(i.dat_w))
) )
] ]

2
artiq/gateware/soc.py
View File

@ -28,7 +28,7 @@ class AMPSoC:
self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram) self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
self.csr_devices.append("kernel_cpu") self.csr_devices.append("kernel_cpu")
self.submodules.mailbox = amp.Mailbox() self.submodules.mailbox = amp.Mailbox(size=3)
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i1) self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),