diff --git a/artiq/gateware/amp/mailbox.py b/artiq/gateware/amp/mailbox.py
index 1addb50ba..6f4a8987f 100644
--- a/artiq/gateware/amp/mailbox.py
+++ b/artiq/gateware/amp/mailbox.py
@@ -3,19 +3,19 @@ from misoc.interconnect import wishbone
 
 
 class Mailbox(Module):
-    def __init__(self):
+    def __init__(self, size=1):
         self.i1 = wishbone.Interface()
         self.i2 = wishbone.Interface()
 
         # # #
 
-        value = Signal(32)
+        values = Array([Signal(32) for _ in range(size)])
         for i in self.i1, self.i2:
             self.sync += [
-                i.dat_r.eq(value),
+                i.dat_r.eq(values[i.adr]),
                 i.ack.eq(0),
                 If(i.cyc & i.stb & ~i.ack,
                     i.ack.eq(1),
-                    If(i.we, value.eq(i.dat_w))
+                    If(i.we, values[i.adr].eq(i.dat_w))
                 )
             ]
diff --git a/artiq/gateware/soc.py b/artiq/gateware/soc.py
index cd567b305..68ae4066a 100644
--- a/artiq/gateware/soc.py
+++ b/artiq/gateware/soc.py
@@ -28,7 +28,7 @@ class AMPSoC:
         self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
         self.csr_devices.append("kernel_cpu")
 
-        self.submodules.mailbox = amp.Mailbox()
+        self.submodules.mailbox = amp.Mailbox(size=3)
         self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
                           self.mailbox.i1)
         self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),