diff --git a/artiq/coredevice/mirny.py b/artiq/coredevice/mirny.py
index a29f57aeb..ddcdd1931 100644
--- a/artiq/coredevice/mirny.py
+++ b/artiq/coredevice/mirny.py
@@ -40,9 +40,8 @@ class Mirny:
     :param refclk: Reference clock (SMA, MMCX or on-board 100 MHz oscillator)
         frequency in Hz
     :param clk_sel: Reference clock selection.
-        valid options are: "XO" - onboard crystal oscillator
-                           "SMA" - front-panel SMA connector
-                           "MMCX" - internal MMCX connector
+        Valid options are: "XO" - onboard crystal oscillator;
+        "SMA" - front-panel SMA connector; "MMCX" - internal MMCX connector.
         Passing an integer writes it as ``clk_sel`` in the CPLD's register 1.
         The effect depends on the hardware revision.
     :param core_device: Core device name (default: "core")
diff --git a/doc/manual/faq.rst b/doc/manual/faq.rst
index 817b64130..bd5d4ac89 100644
--- a/doc/manual/faq.rst
+++ b/doc/manual/faq.rst
@@ -118,4 +118,5 @@ find the dashboard and browser configuration files are stored?
 --------------------------------------------------------------
 
 ::
+
   python -c "from artiq.tools import get_user_config_dir; print(get_user_config_dir())"