mirror of https://github.com/m-labs/artiq.git
Merge pull request #1657 from pathfinder49/phaser
This commit is contained in:
commit
67d474e6cf
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@ -9,8 +9,17 @@ ARTIQ-7
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Highlights:
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* WRPLL
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* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
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* Phaser:
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- Improved documentation
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- Expose the DAC coarse mixer and sif_sync
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- Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
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Breaking changes:
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* Updated Phaser-Upconverter default frequency 2.875 GHz. The new default uses the target PFD
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frequency of the hardware design.
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* `Phaser.init()` now disables all Kasli-oscillators. This avoids full power RF output being
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generated for some configurations.
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* Phaser: fixed coarse mixer frequency configuration
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ARTIQ-6
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@ -110,7 +110,7 @@ class DAC34H84:
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syncsel_mixercd = 0b1001 # sif_sync and register write
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syncsel_nco = 0b1000 # sif_sync
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syncsel_fifo_input = 0b10 # external lvds istr
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sif_sync = 1
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sif_sync = 0
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syncsel_fifoin = 0b0010 # istr
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syncsel_fifoout = 0b0100 # ostr
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@ -178,7 +178,8 @@ class DAC34H84:
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(self.collisiongone_ena << 12) | (self.sif4_ena << 7) |
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(self.mixer_ena << 6) | (self.mixer_gain << 5) |
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(self.nco_ena << 4) | (self.revbus << 3) | (self.twos << 1))
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mmap.append((0x03 << 16) | (self.coarse_dac << 12) | (self.sif_txenable << 0))
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mmap.append((0x03 << 16) | (self.coarse_dac << 12) |
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(self.sif_txenable << 0))
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mmap.append(
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(0x07 << 16) |
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(self.mask_alarm_from_zerochk << 15) | (1 << 14) |
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@ -200,7 +201,7 @@ class DAC34H84:
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mmap.append(
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(0x0d << 16) |
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(self.cmix_fs8 << 15) | (self.cmix_fs4 << 14) |
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(self.cmix_fs2 << 12) | (self.cmix_nfs4 << 11) |
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(self.cmix_fs2 << 13) | (self.cmix_nfs4 << 12) |
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(self.qmc_gainb << 0))
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mmap.append((0x0e << 16) | (self.qmc_gainc << 0))
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mmap.append(
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@ -1,6 +1,8 @@
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from numpy import int32, int64
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from artiq.language.core import kernel, delay_mu, delay
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from artiq.coredevice.rtio import rtio_output, rtio_input_data
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from artiq.language.units import us, ns, ms, MHz, dB
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from artiq.language.units import us, ns, ms, MHz
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from artiq.language.types import TInt32
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from artiq.coredevice.dac34h84 import DAC34H84
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from artiq.coredevice.trf372017 import TRF372017
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@ -84,7 +86,8 @@ class Phaser:
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LVDS bus operating at 1 Gb/s per pin pair and processed in the DAC (Texas
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Instruments DAC34H84). On the DAC 2x interpolation, sinx/x compensation,
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quadrature modulator compensation, fine and coarse mixing as well as group
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delay capabilities are available.
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delay capabilities are available. If desired, these features my be
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configured via the `dac` dictionary.
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The latency/group delay from the RTIO events setting
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:class:`PhaserOscillator` or :class:`PhaserChannel` DUC parameters all the
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@ -184,6 +187,9 @@ class Phaser:
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is_baseband = hw_rev & PHASER_HW_REV_VARIANT
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gw_rev = self.read8(PHASER_ADDR_GW_REV)
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if debug:
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print(gw_rev)
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self.core.break_realtime()
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delay(.1*ms) # slack
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# allow a few errors during startup and alignment since boot
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@ -224,6 +230,8 @@ class Phaser:
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for data in self.dac_mmap:
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self.dac_write(data >> 16, data)
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delay(40*us)
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self.dac_sync()
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delay(40*us)
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# pll_ndivsync_ena disable
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config18 = self.dac_read(0x18)
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@ -272,6 +280,16 @@ class Phaser:
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else:
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raise ValueError("DAC alarm")
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# avoid malformed output for: mixer_ena=1, nco_ena=0 after power up
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self.dac_write(self.dac_mmap[2] >> 16, self.dac_mmap[2] | (1 << 4))
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delay(40*us)
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self.dac_sync()
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delay(100*us)
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self.dac_write(self.dac_mmap[2] >> 16, self.dac_mmap[2])
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delay(40*us)
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self.dac_sync()
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delay(100*us)
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# power up trfs, release att reset
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self.set_cfg(clk_sel=self.clk_sel, dac_txena=0)
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@ -299,6 +317,9 @@ class Phaser:
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self.duc_stb()
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delay(.1*ms) # settle link, pipeline and impulse response
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data = channel.get_dac_data()
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delay(1*us)
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channel.oscillator[0].set_amplitude_phase_mu(asf=0, pow=0xc000,
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clr=1)
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delay(.1*ms)
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sqrt2 = 0x5a81 # 0x7fff/sqrt(2)
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data_i = data & 0xffff
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@ -318,6 +339,7 @@ class Phaser:
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delay(.2*ms)
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for data in channel.trf_mmap:
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channel.trf_write(data)
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channel.cal_trf_vco()
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delay(2*ms) # lock
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if not (self.get_sta() & (PHASER_STA_TRF0_LD << ch)):
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@ -326,6 +348,7 @@ class Phaser:
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if channel.trf_read(0) & 0x1000:
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raise ValueError("TRF R_SAT_ERR")
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delay(.1*ms)
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channel.en_trf_out()
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# enable dac tx
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self.set_cfg(clk_sel=self.clk_sel)
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@ -549,6 +572,48 @@ class Phaser:
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"""
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return self.dac_read(0x06, div=257) >> 8
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@kernel
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def dac_sync(self):
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"""Trigger DAC synchronisation for both output channels.
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The DAC sif_sync is de-asserts, then asserted. The synchronisation is
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triggered on assertion.
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By default, the fine-mixer (NCO) and QMC are synchronised. This
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includes applying the latest register settings.
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The synchronisation sources may be configured through the `syncsel_x`
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fields in the `dac` configuration dictionary (see `__init__()`).
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.. note:: Synchronising the NCO clears the phase-accumulator
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"""
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config1f = self.dac_read(0x1f)
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delay(.1*ms)
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self.dac_write(0x1f, config1f & ~int32(1 << 1))
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self.dac_write(0x1f, config1f | (1 << 1))
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@kernel
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def set_dac_cmix(self, fs_8_step):
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"""Set the DAC coarse mixer frequency for both channels
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Use of the coarse mixer requires the DAC mixer to be enabled. The mixer
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can be configured via the `dac` configuration dictionary (see
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`__init__()`).
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The selected coarse mixer frequency becomes active without explicit
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synchronisation.
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:param fs_8_step: coarse mixer frequency shift in 125 MHz steps. This
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should be an integer between -3 and 4 (inclusive).
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"""
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# values recommended in data-sheet
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# 0 1 2 3 4 -3 -2 -1
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vals = [0b0000, 0b1000, 0b0100, 0b1100, 0b0010, 0b1010, 0b0001, 0b1110]
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cmix = vals[fs_8_step%8]
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config0d = self.dac_read(0x0d)
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delay(.1*ms)
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self.dac_write(0x0d, (config0d & ~(0b1111 << 12)) | (cmix << 12))
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@kernel
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def get_dac_alarms(self):
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"""Read the DAC alarm flags.
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@ -684,6 +749,7 @@ class PhaserChannel:
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self.phaser = phaser
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self.index = index
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self.trf_mmap = TRF372017(trf).get_mmap()
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self.oscillator = [PhaserOscillator(self, osc) for osc in range(5)]
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@kernel
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@ -761,6 +827,12 @@ class PhaserChannel:
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def set_nco_frequency_mu(self, ftw):
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"""Set the NCO frequency.
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This method stages the new NCO frequency, but does not apply it.
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Use of the DAC-NCO requires the DAC mixer and NCO to be enabled. These
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can be configured via the `dac` configuration dictionary (see
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`__init__()`).
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:param ftw: NCO frequency tuning word (32 bit)
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"""
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self.phaser.dac_write(0x15 + (self.index << 1), ftw >> 16)
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@ -770,6 +842,12 @@ class PhaserChannel:
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def set_nco_frequency(self, frequency):
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"""Set the NCO frequency in SI units.
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This method stages the new NCO frequency, but does not apply it.
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Use of the DAC-NCO requires the DAC mixer and NCO to be enabled. These
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can be configured via the `dac` configuration dictionary (see
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`__init__()`).
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:param frequency: NCO frequency in Hz (passband from -400 MHz
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to 400 MHz, wrapping around at +- 500 MHz)
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"""
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@ -780,6 +858,16 @@ class PhaserChannel:
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def set_nco_phase_mu(self, pow):
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"""Set the NCO phase offset.
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By default, the new NCO phase applies on completion of the SPI
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transfer. This also causes a staged NCO frequency to be applied.
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Different triggers for applying nco settings may be configured through
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the `syncsel_mixerxx` fields in the `dac` configuration dictionary (see
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`__init__()`).
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Use of the DAC-NCO requires the DAC mixer and NCO to be enabled. These
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can be configured via the `dac` configuration dictionary (see
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`__init__()`).
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:param pow: NCO phase offset word (16 bit)
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"""
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self.phaser.dac_write(0x12 + self.index, pow)
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@ -788,10 +876,20 @@ class PhaserChannel:
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def set_nco_phase(self, phase):
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"""Set the NCO phase in SI units.
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By default, the new NCO phase applies on completion of the SPI
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transfer. This also causes a staged NCO frequency to be applied.
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Different triggers for applying nco settings may be configured through
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the `syncsel_mixerxx` fields in the `dac` configuration dictionary (see
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`__init__()`).
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Use of the DAC-NCO requires the DAC mixer and NCO to be enabled. These
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can be configured via the `dac` configuration dictionary (see
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`__init__()`).
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:param phase: NCO phase in turns
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"""
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pow = int32(round(phase*(1 << 16)))
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self.set_duc_phase_mu(pow)
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self.set_nco_phase_mu(pow)
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@kernel
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def set_att_mu(self, data):
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@ -886,6 +984,32 @@ class PhaserChannel:
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return self.trf_write(0x00000008 | (cnt_mux_sel << 27),
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readback=True)
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@kernel
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def cal_trf_vco(self):
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"""Start calibration of the upconverter (hardware variant) VCO.
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TRF outputs should be disabled during VCO calibration.
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"""
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self.trf_write(self.trf_mmap[1] | (1 << 31))
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@kernel
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def en_trf_out(self, rf=1, lo=0):
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"""Enable the rf/lo outputs of the upconverter (hardware variant).
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:param rf: 1 to enable RF output, 0 to disable
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:param lo: 1 to enable LO output, 0 to disable
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"""
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data = self.trf_read(0xc)
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delay(0.1 * ms)
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# set RF and LO output bits
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data = data | (1 << 12) | (1 << 13) | (1 << 14)
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# clear to enable output
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if rf == 1:
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data = data ^ (1 << 14)
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if lo == 1:
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data = data ^ ((1 << 12) | (1 << 13))
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self.trf_write(data)
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class PhaserOscillator:
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"""Phaser IQ channel oscillator (NCO/DDS).
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@ -4,20 +4,21 @@ class TRF372017:
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For possible values, documentation, and explanation, see the datasheet.
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https://www.ti.com/lit/gpn/trf372017
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"""
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rdiv = 21 # 13b
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rdiv = 2 # 13b - highest valid f_PFD
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ref_inv = 0
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neg_vco = 1
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icp = 0 # 1.94 mA, 5b
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icp_double = 0
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cal_clk_sel = 12 # /16, 4b
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cal_clk_sel = 0b1110 # div64, 4b
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ndiv = 420 # 16b
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pll_div_sel = 0 # /1, 2b
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prsc_sel = 1 # 8/9
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# default f_vco is 2.875 GHz
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nint = 23 # 16b - lowest value suitable for fractional & integer mode
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pll_div_sel = 0b01 # div2, 2b
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prsc_sel = 0 # 4/5
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vco_sel = 2 # 2b
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vcosel_mode = 0
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cal_acc = 0b00 # 2b
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en_cal = 1
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en_cal = 0 # leave at 0 - calibration is performed in `Phaser.init()`
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nfrac = 0 # 25b
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@ -27,9 +28,9 @@ class TRF372017:
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pwd_vcomux = 0
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pwd_div124 = 0
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pwd_presc = 0
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pwd_out_buff = 1
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pwd_lo_div = 1
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pwd_tx_div = 0
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pwd_out_buff = 1 # leave at 1 - only enable outputs after calibration
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pwd_lo_div = 1 # leave at 1 - only enable outputs after calibration
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pwd_tx_div = 1 # leave at 1 - only enable outputs after calibration
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pwd_bb_vcm = 0
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pwd_dc_off = 0
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en_extvco = 0
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@ -59,8 +60,8 @@ class TRF372017:
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ioff = 0x80 # 8b
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qoff = 0x80 # 8b
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vref_sel = 4 # 0.85 V, 3b
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tx_div_sel = 1 # div2, 2b
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lo_div_sel = 3 # div8, 2b
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tx_div_sel = 0 # div1, 2b
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lo_div_sel = 0 # div1, 2b
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tx_div_bias = 1 # 37.5 µA, 2b
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lo_div_bias = 2 # 50 µA, 2b
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@ -84,6 +85,7 @@ class TRF372017:
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setattr(self, key, value)
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def get_mmap(self):
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"""Memory map for TRF372017"""
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mmap = []
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mmap.append(
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0x9 |
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@ -92,9 +94,10 @@ class TRF372017:
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(self.cal_clk_sel << 27))
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mmap.append(
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0xa |
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(self.ndiv << 5) | (self.pll_div_sel << 21) | (self.prsc_sel << 23) |
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(self.vco_sel << 26) | (self.vcosel_mode << 28) |
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(self.cal_acc << 29) | (self.en_cal << 31))
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(self.nint << 5) | (self.pll_div_sel << 21) |
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(self.prsc_sel << 23) | (self.vco_sel << 26) |
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(self.vcosel_mode << 28) | (self.cal_acc << 29) |
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(self.en_cal << 31))
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mmap.append(0xb | (self.nfrac << 5))
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mmap.append(
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0xc |
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