diff --git a/artiq/gateware/drtio/rt_packets.py b/artiq/gateware/drtio/rt_packets.py
index 4d7037aa7..37570ce3b 100644
--- a/artiq/gateware/drtio/rt_packets.py
+++ b/artiq/gateware/drtio/rt_packets.py
@@ -506,5 +506,35 @@ class RTPacketMaster(Module):
         )
 
         # RX FSM
-        rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM())
+        rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="INPUT"))
         self.submodules += rx_fsm
+
+        echo_reply_now = Signal()
+        self.sync.rtio_rx += self.echo_reply_now.eq(echo_reply_now)
+
+        rx_fsm.act("INPUT",
+            If(rx_dp.frame_r,
+                rx_dp.packet_buffer_load.eq(1),
+                If(rx_dp.packet_last,
+                    Case(rx_dp.packet_type, {
+                        rx_plm.types["error"]: NextState("ERROR"),
+                        rx_plm.types["echo_reply"]: echo_reply_now.eq(1),
+                        rx_plm.types["fifo_level_reply"]: NextState("FIFO_LEVEL"),
+                        "default": [
+                            error_not.eq(1),
+                            error_code.eq(error_codes["unknown_type"])
+                        ]
+                    })
+                )
+            )
+        )
+        rx_fsm.act("ERROR",
+            error_not.eq(1),
+            error_code.eq(rx_dp.packet_as["error"].code),
+            NextState("INPUT")
+        )
+        rx_fsm.act("FIFO_LEVEL",
+            fifo_level_not.eq(1),
+            fifo_level.eq(rx_dp.packet_as["fifo_level_reply"].level),
+            NextState("INPUT")
+        )