From 679060af1db85c00ab049ecea4290a9804d2265f Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Mon, 22 May 2017 19:32:34 +0200 Subject: [PATCH] phaser: enable dma --- artiq/gateware/targets/phaser.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py index 4d7e7309a..f8cddfe0e 100755 --- a/artiq/gateware/targets/phaser.py +++ b/artiq/gateware/targets/phaser.py @@ -149,7 +149,7 @@ class Phaser(MiniSoC, AMPSoC): mem_map = { "cri_con": 0x10000000, "rtio": 0x20000000, - # "rtio_dma": 0x30000000, + "rtio_dma": 0x30000000, "mailbox": 0x70000000, "ad9154": 0x50000000, } @@ -225,12 +225,12 @@ class Phaser(MiniSoC, AMPSoC): self.submodules.rtio_core = rtio.Core(rtio_channels) self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator() - # self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( - # rtio.DMA(self.get_native_sdram_if())) + self.submodules.rtio_dma = ClockDomainsRenamer("sys_kernel")( + rtio.DMA(self.get_native_sdram_if())) self.register_kernel_cpu_csrdevice("rtio") - # self.register_kernel_cpu_csrdevice("rtio_dma") + self.register_kernel_cpu_csrdevice("rtio_dma") self.submodules.cri_con = rtio.CRIInterconnectShared( - [self.rtio.cri], # , self.rtio_dma.cri], + [self.rtio.cri, self.rtio_dma.cri], [self.rtio_core.cri]) self.register_kernel_cpu_csrdevice("cri_con") self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)