diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py
index cc92d45a2..25048f849 100755
--- a/artiq/gateware/targets/kc705_dds.py
+++ b/artiq/gateware/targets/kc705_dds.py
@@ -100,9 +100,9 @@ _ams101_dac = [
 
 class _NIST_Ions(MiniSoC, AMPSoC):
     mem_map = {
+        "cri_con":       0x10000000,
         "rtio":          0x20000000,
         "rtio_dma":      0x30000000,
-        "cri_con":       0x50000000,
         "mailbox":       0x70000000
     }
     mem_map.update(MiniSoC.mem_map)
diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py
index f41e2fafc..6de5a5838 100755
--- a/artiq/gateware/targets/kc705_drtio_master.py
+++ b/artiq/gateware/targets/kc705_drtio_master.py
@@ -21,6 +21,7 @@ from artiq import __version__ as artiq_version
 
 class Master(MiniSoC, AMPSoC):
     mem_map = {
+        "cri_con":       0x10000000,
         "rtio":          0x20000000,
         "rtio_dma":      0x30000000,
         "drtio_aux":     0x50000000,
@@ -114,6 +115,7 @@ class Master(MiniSoC, AMPSoC):
         self.submodules.cri_con = rtio.CRIInterconnectShared(
             [self.rtio.cri, self.rtio_dma.cri],
             [self.rtio_core.cri, self.drtio.cri])
+        self.register_kernel_cpu_csrdevice("cri_con")
 
 
 def main():
diff --git a/artiq/gateware/targets/phaser.py b/artiq/gateware/targets/phaser.py
index d357ff04b..9d6674ac3 100755
--- a/artiq/gateware/targets/phaser.py
+++ b/artiq/gateware/targets/phaser.py
@@ -156,6 +156,7 @@ class AD9154(Module, AutoCSR):
 
 class Phaser(MiniSoC, AMPSoC):
     mem_map = {
+        "cri_con":       0x10000000,
         "rtio":          0x20000000,
         # "rtio_dma":      0x30000000,
         "mailbox":       0x70000000,
@@ -240,6 +241,7 @@ class Phaser(MiniSoC, AMPSoC):
         self.submodules.cri_con = rtio.CRIInterconnectShared(
             [self.rtio.cri],  # , self.rtio_dma.cri],
             [self.rtio_core.cri])
+        self.register_kernel_cpu_csrdevice("cri_con")
         self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
         self.csr_devices.append("rtio_moninj")
         self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_core.cri,