From 66d1647efd51a9eaf91226f7c6993e03fbab4fb4 Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Fri, 29 Dec 2017 01:40:31 +0800
Subject: [PATCH] spi: register clk

---
 artiq/gateware/spi.py | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/artiq/gateware/spi.py b/artiq/gateware/spi.py
index 2daa3907c..448d22d03 100644
--- a/artiq/gateware/spi.py
+++ b/artiq/gateware/spi.py
@@ -208,9 +208,11 @@ class SPIMaster(Module):
 
         clk_t = TSTriple()
         self.specials += clk_t.get_tristate(pads.clk)
-        self.comb += [
-            clk_t.oe.eq(~config.offline),
-            clk_t.o.eq((spi.cg.clk & spi.cs) ^ config.clk_polarity),
+        self.comb += clk_t.oe.eq(~config.offline),
+        self.sync += [
+            If(spi.cg.ce & spi.cg.edge,
+                clk_t.o.eq((~spi.cg.clk & spi.cs_next) ^ config.clk_polarity)
+            )
         ]
 
         mosi_t = TSTriple()