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ttl/clockgen: expose acc_width

pull/109/head
Sebastien Bourdeauducq 2015-07-04 19:21:25 +02:00
parent abd58667b9
commit 65ec6c28f4
1 changed files with 3 additions and 2 deletions
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5
artiq/coredevice/ttl.py
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@ -224,20 +224,21 @@ class TTLClockGen(AutoDB):
def build(self):
# in RTIO cycles
self.previous_timestamp = int64(0)
self.acc_width = 24
@portable
def frequency_to_ftw(self, frequency):
"""Returns the frequency tuning word corresponding to the given
frequency.
"""
return round(2**24*frequency*self.core.ref_period)
return round(2**self.acc_width*frequency*self.core.ref_period)
@portable
def ftw_to_frequency(self, ftw):
"""Returns the frequency corresponding to the given frequency tuning
word.
"""
return ftw/self.core.ref_period/2**24
return ftw/self.core.ref_period/2**self.acc_width
@kernel
def set_mu(self, frequency):