From 65baca8c57a6933eb35f41aa1d6d5ef9c98d6fc9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 17 Sep 2017 16:11:36 +0800 Subject: [PATCH] rtio: clean up error-prone rtlink.get_or_zero() --- artiq/gateware/rtio/core.py | 6 ++++-- artiq/gateware/rtio/rtlink.py | 13 ++++++------- artiq/gateware/rtio/sed/core.py | 2 +- artiq/gateware/rtio/sed/layouts.py | 10 +++++----- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index 8492e31f4..ea390bd2c 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -190,8 +190,10 @@ class Core(Module, AutoCSR): self.specials += AsyncResetSynchronizer(self.cd_rio_phy, cmd_reset_phy) # TSC - fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface) - for channel in channels) + fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o) + for channel in channels), + max(rtlink.get_fine_ts_width(channel.interface.i) + for channel in channels)) coarse_ts = Signal(64-fine_ts_width) self.sync.rtio += coarse_ts.eq(coarse_ts + 1) coarse_ts_cdc = GrayCodeTransfer(len(coarse_ts)) diff --git a/artiq/gateware/rtio/rtlink.py b/artiq/gateware/rtio/rtlink.py index a4fb3ebf9..06cc0ebf2 100644 --- a/artiq/gateware/rtio/rtlink.py +++ b/artiq/gateware/rtio/rtlink.py @@ -69,14 +69,13 @@ class Interface: def _get_or_zero(interface, attr): - if isinstance(interface, Interface): - return max(_get_or_zero(interface.i, attr), - _get_or_zero(interface.o, attr)) + if interface is None: + return 0 + assert isinstance(interface, (OInterface, IInterface)) + if hasattr(interface, attr): + return len(getattr(interface, attr)) else: - if hasattr(interface, attr): - return len(getattr(interface, attr)) - else: - return 0 + return 0 def get_data_width(interface): diff --git a/artiq/gateware/rtio/sed/core.py b/artiq/gateware/rtio/sed/core.py index 30f16a863..55a068c4b 100644 --- a/artiq/gateware/rtio/sed/core.py +++ b/artiq/gateware/rtio/sed/core.py @@ -27,7 +27,7 @@ class SED(Module): else: raise ValueError - fine_ts_width = max(rtlink.get_fine_ts_width(c.interface) + fine_ts_width = max(rtlink.get_fine_ts_width(c.interface.o) for c in channels) seqn_width = layouts.seqn_width(lane_count, fifo_depth) diff --git a/artiq/gateware/rtio/sed/layouts.py b/artiq/gateware/rtio/sed/layouts.py index b0a983911..b49e1139b 100644 --- a/artiq/gateware/rtio/sed/layouts.py +++ b/artiq/gateware/rtio/sed/layouts.py @@ -4,9 +4,9 @@ from artiq.gateware.rtio import rtlink def fifo_payload(channels): - address_width = max(rtlink.get_address_width(channel.interface) + address_width = max(rtlink.get_address_width(channel.interface.o) for channel in channels) - data_width = max(rtlink.get_data_width(channel.interface) + data_width = max(rtlink.get_data_width(channel.interface.o) for channel in channels) layout = [ @@ -46,11 +46,11 @@ def fifo_egress(seqn_width, layout_payload): def output_network_payload(channels): - fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface) + fine_ts_width = max(rtlink.get_fine_ts_width(channel.interface.o) for channel in channels) - address_width = max(rtlink.get_address_width(channel.interface) + address_width = max(rtlink.get_address_width(channel.interface.o) for channel in channels) - data_width = max(rtlink.get_data_width(channel.interface) + data_width = max(rtlink.get_data_width(channel.interface.o) for channel in channels) layout = [("channel", bits_for(len(channels)-1))]