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phaser: sysref/sync diff term

This commit is contained in:
Robert Jördens 2016-10-27 14:14:56 +02:00
parent 062aca2a6b
commit 65b2e4464c
1 changed files with 3 additions and 0 deletions
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3
artiq/gateware/phaser.py
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@ -25,16 +25,19 @@ fmc_adapter_io = [
Subsignal("p", Pins("HPC:LA00_CC_P")), Subsignal("p", Pins("HPC:LA00_CC_P")),
Subsignal("n", Pins("HPC:LA00_CC_N")), Subsignal("n", Pins("HPC:LA00_CC_N")),
IOStandard("LVDS_25"), IOStandard("LVDS_25"),
Misc("DIFF_TERM=TRUE"),
), ),
("ad9154_sync", 0, ("ad9154_sync", 0,
Subsignal("p", Pins("HPC:LA01_CC_P")), Subsignal("p", Pins("HPC:LA01_CC_P")),
Subsignal("n", Pins("HPC:LA01_CC_N")), Subsignal("n", Pins("HPC:LA01_CC_N")),
IOStandard("LVDS_25"), IOStandard("LVDS_25"),
Misc("DIFF_TERM=TRUE"),
), ),
("ad9154_sync", 1, ("ad9154_sync", 1,
Subsignal("p", Pins("HPC:LA02_P")), Subsignal("p", Pins("HPC:LA02_P")),
Subsignal("n", Pins("HPC:LA02_N")), Subsignal("n", Pins("HPC:LA02_N")),
IOStandard("LVDS_25"), IOStandard("LVDS_25"),
Misc("DIFF_TERM=TRUE"),
), ),
("ad9154_jesd", 0, # AD9154's SERIND7 ("ad9154_jesd", 0, # AD9154's SERIND7
Subsignal("txp", Pins("HPC:DP0_C2M_P")), Subsignal("txp", Pins("HPC:DP0_C2M_P")),